AN 805: Hierarchical Partial Reconfiguration of a Design on Intel® Arria® 10 SoC Development Board

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ID 683409
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board
Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Sub-module Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core Step 6: Defining Personas Step 7: Creating Revisions Step 8: Generating the Hierarchical Partial Reconfiguration Flow Script Step 9: Running the Hierarchical Partial Reconfiguration Flow Script Step 10: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core x
Updating the Top-Level Design
Step 7: Creating Revisions x
Creating Implementation Revisions Creating Synthesis-Only Revisions Specifying Revision Type
Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board

Step 10: Programming the Board

Before you begin:
  1. Connect the power supply to the Intel® Arria® 10 SoC development board.
  2. Connect the USB Blaster cable between your PC USB port and the USB Blaster port on the development board.

To run the design on the Intel® Arria® 10 SoC development board:

  1. Open the Intel® Quartus® Prime software and click Tools > Programmer.
  2. In the Programmer, click Hardware Setup and select USB-Blaster.
  3. Click Auto Detect and select the device, 10AS066N3.
  4. Click OK. The Intel® Quartus® Prime software detects and updates the Programmer with the three FPGA chips on the board.
  5. Select the 10AS066N3 device, click Change File and load the blinking_led_pr_alpha.sof file.
  6. Enable Program/Configure for blinking_led_pr_alpha.sof file.
  7. Click Start and wait for the progress bar to reach 100%.
  8. Observe the LEDs on the board blinking at the same frequency as the original flat design.
  9. To program only the child PR region, right-click the blinking_led_pr_alpha.sof file in the Programmer and click Add PR Programming File.
  10. Select the blinking_led_pr_bravo.pr_parent_partition.pr_partition.rbf file.
  11. Disable Program/Configure for blinking_led_pr_alpha.sof file.
  12. Enable Program/Configure for blinking_led_pr_bravo.pr_parent_partition.pr_partition.rbf file and click Start. On the board, observe LED[0] and LED[1] continuing to blink. When the progress bar reaches 100%, LED[2] blinks at the same rate, and LED[3] blinks slower.
  13. To program both the parent and child PR region, right-click the .rbf file in the Programmer and click Change PR Programing File.
  14. Select the blinking_led_pr_delta.pr_parent_partition.rbf file.
  15. Click Start. On the board, observe that LED[0] and LED[1] continuing to blink. When the progress bar reaches 100%, both LED[2] and LED[3] blink slower.
  16. Repeat the above steps to dynamically re-program just the child PR region, or both the parent and child PR regions simultaneously.
Figure 10. Programming the Intel® Arria® 10 SoC Development Board
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