AN 805: Hierarchical Partial Reconfiguration of a Design on Intel® Arria® 10 SoC Development Board

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ID 683409
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board
Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Sub-module Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core Step 6: Defining Personas Step 7: Creating Revisions Step 8: Generating the Hierarchical Partial Reconfiguration Flow Script Step 9: Running the Hierarchical Partial Reconfiguration Flow Script Step 10: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core x
Updating the Top-Level Design
Step 7: Creating Revisions x
Creating Implementation Revisions Creating Synthesis-Only Revisions Specifying Revision Type
Hierarchical Partial Reconfiguration Tutorial for Intel® Arria® 10 SoC Development Board

Reference Design Files

The partial reconfiguration tutorial is available in the following location:

https://github.com/intel/fpga-partial-reconfig

To download the tutorial:
  1. Click Clone or download.
  2. Click Download ZIP. Unzip the fpga-partial-reconfig-master.zip file.
  3. Navigate to the tutorials/a10_soc_devkit_blinking_led_hpr sub-folder to access the reference design.
The flat folder consists of the following files:
Table 1.  Reference Design Files
File Name Description
top.sv

Top-level file containing the flat implementation of the design. This module instantiates the blinking_led sub-partition and the top_counter module.

top_counter.sv Top-level 32-bit counter that controls LED[1] directly. The registered output of the counter controls LED[0], and also powers LED[2] and LED[3] via the blinking_led module.
blinking_led.sdc

Defines the timing constraints for the project.
blinking_led.sv In this tutorial, you convert this module into a parent PR partition. The module receives the registered output of top_counter module, which controls LED[2] and LED[3].
blinking_led.qpf

Intel® Quartus® Prime project file containing the list of all the revisions in the project.

blinking_led.qsf

Intel® Quartus® Prime settings file containing the assignments and settings for the project.

Note: The hpr folder contains the complete set of files you create using this application note. Reference these files at any point during the walkthrough.
Figure 2. Reference Design Files
Level Two Title