Visible to Intel only — GUID: zby1488919227877
Ixiasoft
Step 1: Getting Started
Step 2: Creating a Child Level Sub-module
Step 3: Creating Design Partitions
Step 4: Allocating Placement and Routing Region for PR Partitions
Step 5: Adding the Intel® Arria® 10 Partial Reconfiguration Controller IP Core
Step 6: Defining Personas
Step 7: Creating Revisions
Step 8: Generating the Hierarchical Partial Reconfiguration Flow Script
Step 9: Running the Hierarchical Partial Reconfiguration Flow Script
Step 10: Programming the Board
Modifying an Existing Persona
Adding a New Persona to the Design
Visible to Intel only — GUID: zby1488919227877
Ixiasoft
Step 7: Creating Revisions
The PR design flow uses the project revisions feature in the Intel® Quartus® Prime software. Your initial design is the base revision, where you define the static region boundaries and reconfigurable regions on the FPGA. From the base revision, you create multiple revisions. These revisions contain the different implementations for the PR regions. However, all PR implementation revisions use the same top-level placement and routing results from the base revision.
To compile a PR design, you must create a PR implementation revision and synthesis revision for each persona. In this reference design, in addition to the base revision (blinking_led), the three child-level personas and the two parent-level personas contain five separate synthesis revisions, and five separate implementation revisions:
| Synthesis Revision | Implementation Revision |
|---|---|
| blinking_led_parent, blinking_led_default | blinking_led_pr_alpha |
| blinking_led_parent, blinking_led_child_slow | blinking_led_pr_bravo |
| blinking_led_parent, blinking_led_child_empty | blinking_led_pr_charlie |
| blinking_led_parent_slow, blinking_led_child_slow | blinking_led_pr_delta |
| blinking_led_parent_slow, blinking_led_child_empty | blinking_led_pr_emma |