Intel® FPGA SDK for OpenCL™ Standard Edition: Custom Platform Toolkit User Guide

Download PDF
ID 683398
Date 5/04/2018
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit User Guide 2. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit Reference Material
1. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit User Guide x
1.1. Prerequisites for the Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit 1.2. Overview of the Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform 1.3. Custom Platform Automigration for Forward Compatibility 1.4. Creating an Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform 1.5. Applying for the Intel® FPGA SDK for OpenCL™ Standard Edition Preferred Board Status 1.6. Shipping Recommendations 1.7. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Design Revision History
1.2. Overview of the Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform x
1.2.1. Directories and Files in an Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform 1.2.2. Recommendations for Structuring the Custom Platform Directory
1.3. Custom Platform Automigration for Forward Compatibility x
1.3.1. Customizing Automigration
1.4. Creating an Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform x
1.4.1. Designing the Board Hardware 1.4.2. Creating the Board XML Files 1.4.3. Creating the MMD Library 1.4.4. Setting Up the FPGA Client Driver 1.4.5. Providing Intel® FPGA SDK for OpenCL™ Standard Edition Utilities Support 1.4.6. Testing the Hardware Design
1.4.1. Designing the Board Hardware x
1.4.1.1. Creating the Board Platform Designer (Standard) System 1.4.1.2. Establishing Guaranteed Timing Flow
1.4.1.1. Creating the Board Platform Designer (Standard) System x
1.4.1.1.1. General Quality of Results Considerations for the Exported Board Partition
1.4.2. Creating the Board XML Files x
1.4.2.1. Creating the board_env.xml File 1.4.2.2. Creating the board_spec.xml File
1.4.2.1. Creating the board_env.xml File x
1.4.2.1.1. Testing the board_env.xml File
1.4.3. Creating the MMD Library x
1.4.3.1. Kernel Power-up State
2. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit Reference Material x
2.1. The Board Platform Designer (Standard) Subsystem 2.2. XML Elements, Attributes, and Parameters in the board_spec.xml File 2.3. MMD API Descriptions 2.4. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit Reference Manual Revision History
2.1. The Board Platform Designer (Standard) Subsystem x
2.1.1. Intel® FPGA SDK for OpenCL™ Standard Edition-Specific Platform Designer (Standard) System Components
2.1.1. Intel® FPGA SDK for OpenCL™ Standard Edition-Specific Platform Designer (Standard) System Components x
2.1.1.1. OpenCL Kernel Clock Generator 2.1.1.2. OpenCL Kernel Interface 2.1.1.3. OpenCL Memory Bank Divider
2.2. XML Elements, Attributes, and Parameters in the board_spec.xml File x
2.2.1. board 2.2.2. device 2.2.3. global_mem 2.2.4. host 2.2.5. channels 2.2.6. interfaces 2.2.7. interface 2.2.8. compile
2.3. MMD API Descriptions x
2.3.1. aocl_mmd_get_offline_info 2.3.2. aocl_mmd_get_info 2.3.3. aocl_mmd_open 2.3.4. aocl_mmd_close 2.3.5. aocl_mmd_read 2.3.6. aocl_mmd_write 2.3.7. aocl_mmd_copy 2.3.8. aocl_mmd_set_interrupt_handler 2.3.9. aocl_mmd_set_status_handler 2.3.10. aocl_mmd_yield 2.3.11. aocl_mmd_shared_mem_alloc 2.3.12. aocl_mmd_shared_mem_free 2.3.13. aocl_mmd_reprogram 2.3.14. aocl_mmd_hostchannel_create 2.3.15. aocl_mmd_hostchannel_destroy 2.3.16. aocl_mmd_hostchannel_get_buffer 2.3.17. aocl_mmd_hostchannel_ack_buffer
2.3.13. aocl_mmd_reprogram x
2.3.13.1. Reprogram Support
1. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit User Guide
2. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit Reference Material

2.1.1.2. OpenCL Kernel Interface

The OpenCL™ Kernel Interface is a Platform Designer (Standard) component that allows the host interface to access and control the OpenCL kernel.
Table 7.  Parameter Settings for the OpenCL Kernel Interface Component
Parameter Description
Number of global memory systems Number of global memory types in your board design.
Table 8.  Signals and Ports for the OpenCL Kernel Interface Component
Signal or Port Description
clk The clock input used for the host control interface. The clock rate of clk can be slow.
reset This reset input resets the control interface. It also triggers the kernel_reset signal, which resets all kernel logic.
kernel_ctrl Use this slave port to connect to the OpenCL host interface. This interface is a low-speed interface with which you set kernel arguments and start the kernel's execution.
kernel_clk The kernel_clk output from the OpenCL Kernel Clock Generator drives this clock input.
kernel_cra This Avalon®-MM master interface communicates directly with the kernels generated by the Intel® FPGA SDK for OpenCL™ Offline Compiler. Export the Avalon-MM interface to the OpenCL Kernel Interface and name it in the board_spec.xml file.
sw_reset_in When necessary, the OpenCL host interface resets the kernel via the kernel_ctrl interface. If the board design requires a kernel reset, it can do so via this reset input. Otherwise, connect the interface to a global power-on reset.
kernel_reset Use this reset output to reset the kernel and any other hardware that communicates with the kernel.
Warning: This reset occurs between the MMD open and close calls. Therefore, it must not reset anything necessary for the operation of your MMD.
sw_reset_export This reset output is the same as kernel_reset, but it is synchronized to the clk interface. Use this output to reset logic that is not in the kernel_clk clock domain but should be reset whenever the kernel resets.
acl_bsp_memorg_host The memory interfaces use these signals.

Based on the number of global memory systems you specify in the OpenCL Kernel Interface component parameter editor, the Intel® Quartus® Prime Standard Edition software creates the corresponding number of copies of this signal, each with a different hexadecimal suffix. Connect each signal to the OpenCL Memory Bank Divider component associated with each global memory system (for example, DDR). Then, list the hexadecimal suffix in the config_addr attribute of the global_mem element in the board_spec.xml file.

kernel_irq_from_kernel An interrupt input from the kernel. This signal will be exported and named in the board_spec.xml file.
kernel_irq_to_host An interrupt output from the kernel. This signal will connect to the host interface.
Level Two Title