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1.1. Prerequisites for the Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit
1.2. Overview of the Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform
1.3. Custom Platform Automigration for Forward Compatibility
1.4. Creating an Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform
1.5. Applying for the Intel® FPGA SDK for OpenCL™ Standard Edition Preferred Board Status
1.6. Shipping Recommendations
1.7. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Design Revision History
2.3.1. aocl_mmd_get_offline_info
2.3.2. aocl_mmd_get_info
2.3.3. aocl_mmd_open
2.3.4. aocl_mmd_close
2.3.5. aocl_mmd_read
2.3.6. aocl_mmd_write
2.3.7. aocl_mmd_copy
2.3.8. aocl_mmd_set_interrupt_handler
2.3.9. aocl_mmd_set_status_handler
2.3.10. aocl_mmd_yield
2.3.11. aocl_mmd_shared_mem_alloc
2.3.12. aocl_mmd_shared_mem_free
2.3.13. aocl_mmd_reprogram
2.3.14. aocl_mmd_hostchannel_create
2.3.15. aocl_mmd_hostchannel_destroy
2.3.16. aocl_mmd_hostchannel_get_buffer
2.3.17. aocl_mmd_hostchannel_ack_buffer
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1.4.1.1.1. General Quality of Results Considerations for the Exported Board Partition
When generating a post-place-and-route partition, take into account several design considerations for the exported board partition that might have unexpected consequences on the Intel® FPGA SDK for OpenCL™ Standard Edition compilation results. The best approach to optimizing the board partition is to experiment with a range of different OpenCL kernels.
The list below captures some of the parameters that might impact the quality of SDK compilation results:
- Resources Used
Minimize the number of resources the partition uses to maximize the resources available for the OpenCL kernels.
- Kernel Clock Frequency
Intel® recommends that the kernel clock has a high clock constraint (for example, greater than 350 MHz for a Stratix® V device). The amount of logic in the partition clocked by the kernel clock should be relatively small. This logic should not limit the kernel clock speed for even the simplest OpenCL kernels. Therefore, at least within the partition, the kernel clock should have a high clock constraint.
- Host-to-Memory Bandwidth
The host-to-memory bandwidth is the transfer speed between the host processor to the physical memories on the accelerator card. To measure this memory bandwidth, compile and run the host application included with the Custom Platform Toolkit.
- Kernel-to-Memory Bandwidth
The kernel-to-memory bandwidth is the maximum transfer speed possible between the OpenCL kernels and global memory.
To measure this memory bandwidth, compile and run the host program included in the /tests/boardtest/host directory of the Custom Platform Toolkit.
- Fitter Quality of Results (QoR)
To ensure that OpenCL designs consuming much of the device's resources can still achieve high clock frequencies, region-constrain the partition to the edges of the FPGA. The constraint allows OpenCL kernel logic to occupy the center of the device, which has the most connectivity with all other nodes.
Test compile large designs to ensure that other Fitter-induced artifacts in the partition do not interfere with the QoR of the kernel compilations.
- Routability
The routing resources that the partition consumes can affect the routability of a compiled OpenCL design. A kernel might use every digital signal processing (DSP) block or memory block on the FPGA; however, routing resources that the partition uses might render one of these blocks unroutable. This routing issue causes compilation of the Intel® Quartus® Prime project to fail at the fitting step. Therefore, it is imperative that you test a partition with designs that use all DSP and memory blocks.