AN 904: Intel® MAX® 10 Hitless Update Implementation Guidelines

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ID 683380
Date 5/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Hitless Update Implementation Guidelines
1. Intel® MAX® 10 Hitless Update Implementation Guidelines x
1.1. Introduction 1.2. Types of Intel® MAX® 10 Design Update Flow 1.3. Stages of Intel® MAX® 10 Hitless Update Flow 1.4. Intel® MAX® 10 Hitless Update Requirement and Limitation 1.5. Hitless Update using Intel® Quartus® Prime Programmer 1.6. Hitless Update using Intel® Jam STAPL Byte-Code Player 1.7. Hitless Update Using Self-Developed Algorithm 1.8. Boundary-Scan Pattern Configuration Bit Location 1.9. JTAG Instructions 1.10. Sample of Hitless Update Algorithm in Jam Format 1.11. Document Revision History for AN 904: Intel® MAX® 10 Hitless Update Implementation Guidelines
1.5. Hitless Update using Intel® Quartus® Prime Programmer x
1.5.1. Creating IPS File 1.5.2. Executing IPS File
1.6. Hitless Update using Intel® Jam STAPL Byte-Code Player x
1.6.1. Generating .jam/.jbc File 1.6.2. Interpreting Jam File Information using Jam Player
1.7. Hitless Update Using Self-Developed Algorithm x
1.7.1. Custom Algorithm Implementation Flow for Intel® MAX® 10 Devices with SC/SA/SL/DC/DF/DA Feature Options 1.7.2. Custom Algorithm Implementation Flow for Intel® MAX® 10 Devices with DD Feature Option
1. Intel® MAX® 10 Hitless Update Implementation Guidelines

1.1. Introduction

Intel® MAX® 10 devices offer the hitless update feature, which provides you the capability and flexibility to control the state of the I/O pins during the internal flash image update and reconfiguration of an Intel® MAX® 10 device. All of the I/O pins can remain stable without any disruption throughout the hitless update process. This feature also allows the Intel® MAX® 10 device to behave as a system controller when monitoring and controlling critical signals without interruption.

These guidelines help you implement the hitless update through Intel® Quartus® Prime Programmer or the Intel® Jam™ Standard Test and Programming Language (STAPL) Byte-Code Player. These guidelines also provide the details of the hitless update flow to enable you to develop your own source code to implement the hitless update through your microprocessor or external host.

The guidelines in this application note are for hitless update using external JTAG pins. For hitless update using internal JTAG interface, refer to AN 963: Intel® MAX® 10 Hitless Update Implementation Guidelines using Internal JTAG Interface.

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