AN 904: Intel® MAX® 10 Hitless Update Implementation Guidelines

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ID 683380
Date 5/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Hitless Update Implementation Guidelines
1. Intel® MAX® 10 Hitless Update Implementation Guidelines x
1.1. Introduction 1.2. Types of Intel® MAX® 10 Design Update Flow 1.3. Stages of Intel® MAX® 10 Hitless Update Flow 1.4. Intel® MAX® 10 Hitless Update Requirement and Limitation 1.5. Hitless Update using Intel® Quartus® Prime Programmer 1.6. Hitless Update using Intel® Jam STAPL Byte-Code Player 1.7. Hitless Update Using Self-Developed Algorithm 1.8. Boundary-Scan Pattern Configuration Bit Location 1.9. JTAG Instructions 1.10. Sample of Hitless Update Algorithm in Jam Format 1.11. Document Revision History for AN 904: Intel® MAX® 10 Hitless Update Implementation Guidelines
1.5. Hitless Update using Intel® Quartus® Prime Programmer x
1.5.1. Creating IPS File 1.5.2. Executing IPS File
1.6. Hitless Update using Intel® Jam STAPL Byte-Code Player x
1.6.1. Generating .jam/.jbc File 1.6.2. Interpreting Jam File Information using Jam Player
1.7. Hitless Update Using Self-Developed Algorithm x
1.7.1. Custom Algorithm Implementation Flow for Intel® MAX® 10 Devices with SC/SA/SL/DC/DF/DA Feature Options 1.7.2. Custom Algorithm Implementation Flow for Intel® MAX® 10 Devices with DD Feature Option
1. Intel® MAX® 10 Hitless Update Implementation Guidelines

1.8. Boundary-Scan Pattern Configuration Bit Location

The length of the boundary-scan pattern shifted out from the boundary-scan cell varies between different device densities. Hence, the position of configuration bits, such as nSTATUS and CONF_DONE, is different. In the boundary-scan data, each pin has three control bits to control the settings of the I/O pin:
  • Input bit
  • OE bit
  • Output bit

Updating the configuration bits state within the boundary-scan data is a critical step to ensure that the entire hitless update process is works flawlessly. You must know the configuration bit position within the boundary-scan data based on the device used.

Table 1.  Configuration Bit Position Based on Intel® MAX® 10 Device Densities
Device Configuration Bit Position Total Boundary-Scan Chain Bits
10M02

nSTATUS: Input bit (bit 21), OE bit (bit 22), Output bit (bit 23)

CONF_DONE: Input bit (bit 12), OE bit (bit 13), Output bit (bit 14)

492
10M04

nSTATUS: Input bit (bit 21), OE bit (bit 22), Output bit (bit 23)

CONF_DONE: Input bit (bit 12), OE bit (bit 13), Output bit (bit 14)

756
10M08

nSTATUS: Input bit (bit 21), OE bit (bit 22), Output bit (bit 23)

CONF_DONE: Input bit (bit 12), OE bit (bit 13), Output bit (bit 14)

756
10M16

nSTATUS: Input bit (bit 21), OE bit (bit 22), Output bit (bit 23)

CONF_DONE: Input bit (bit 12), OE bit (bit 13), Output bit (bit 14)

960
10M25

nSTATUS: Input bit (bit 21), OE bit (bit 22), Output bit (bit 23)

CONF_DONE: Input bit (bit 12), OE bit (bit 13), Output bit (bit 14)

1140
10M40

nSTATUS: Input bit (bit 21), OE bit (bit 22), Output bit (bit 23)

CONF_DONE: Input bit (bit 12), OE bit (bit 13), Output bit (bit 14)

1500
10M50

nSTATUS: Input bit (bit 21), OE bit (bit 22), Output bit (bit 23)

CONF_DONE: Input bit (bit 12), OE bit (bit 13), Output bit (bit 14)

1500
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