AN 904: Intel® MAX® 10 Hitless Update Implementation Guidelines

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ID 683380
Date 5/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Hitless Update Implementation Guidelines
1. Intel® MAX® 10 Hitless Update Implementation Guidelines x
1.1. Introduction 1.2. Types of Intel® MAX® 10 Design Update Flow 1.3. Stages of Intel® MAX® 10 Hitless Update Flow 1.4. Intel® MAX® 10 Hitless Update Requirement and Limitation 1.5. Hitless Update using Intel® Quartus® Prime Programmer 1.6. Hitless Update using Intel® Jam STAPL Byte-Code Player 1.7. Hitless Update Using Self-Developed Algorithm 1.8. Boundary-Scan Pattern Configuration Bit Location 1.9. JTAG Instructions 1.10. Sample of Hitless Update Algorithm in Jam Format 1.11. Document Revision History for AN 904: Intel® MAX® 10 Hitless Update Implementation Guidelines
1.5. Hitless Update using Intel® Quartus® Prime Programmer x
1.5.1. Creating IPS File 1.5.2. Executing IPS File
1.6. Hitless Update using Intel® Jam STAPL Byte-Code Player x
1.6.1. Generating .jam/.jbc File 1.6.2. Interpreting Jam File Information using Jam Player
1.7. Hitless Update Using Self-Developed Algorithm x
1.7.1. Custom Algorithm Implementation Flow for Intel® MAX® 10 Devices with SC/SA/SL/DC/DF/DA Feature Options 1.7.2. Custom Algorithm Implementation Flow for Intel® MAX® 10 Devices with DD Feature Option
1. Intel® MAX® 10 Hitless Update Implementation Guidelines

1.7.2. Custom Algorithm Implementation Flow for Intel® MAX® 10 Devices with DD Feature Option

You can implement the hitless update in Intel® MAX® 10 devices through JTAG Instructions by sampling the existing I/O states and retain the I/O states across the entire configuration flow.

For Intel® MAX® 10 devices with DD feature option, reconfiguration is triggered automatically after ISP mode is disabled.

To implement the hitless update, perform the following steps:

  1. Shift in desired I/O state or maintain existing I/O state into boundary scan through SAMPLE/PRELOAD JTAG instruction.
  2. Enter ISP mode with the ISP_ENABLE_CLAMP instruction and stay in the RUNTEST IDLE state for at least 10 TCK pulses.
  3. Perform an internal flash read or write operation through the ISP_PROGRAM and ISP_READ instructions.
    Note: To obtain the Programming Specification, contact Intel Premier Support and quote ID #1509940684.
  4. Disable ISP mode with the ISP_DISABLE instruction and stay in the RUNTEST IDLE state for at least 10 TCK pulses. Reconfiguration is triggered after disable ISP mode.
  5. Exit ISP mode with the EXTEST instruction, and stay in the RUNTEST IDLE state for at least 10 TCK pulses. Wait for device initialization and internal configuration (refer to the Internal Configuration Time for Intel® MAX® 10 Devices (Uncompressed .rbf) and Internal Configuration Time for Intel® MAX® 10 Devices (Compressed .rbf) tables in the Intel® MAX® 10 FPGA Device Datasheet for internal configuration time).
  6. Wait for start-up (refer to the Internal Configuration Timing Parameter for Intel® MAX® 10 Devices table in the Intel® MAX® 10 FPGA Device Datasheet for start-up time). Device enters user mode. The design core is running now but I/O state is still clamped.
  7. Disable EXTEST with JTAG TAP RESET to release the I/O clamp. You can insert any amount of delay before performing JTAG TAP RESET to release the clamp.
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