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1.1. Introduction
1.2. Types of Intel® MAX® 10 Design Update Flow
1.3. Stages of Intel® MAX® 10 Hitless Update Flow
1.4. Intel® MAX® 10 Hitless Update Requirement and Limitation
1.5. Hitless Update using Intel® Quartus® Prime Programmer
1.6. Hitless Update using Intel® Jam STAPL Byte-Code Player
1.7. Hitless Update Using Self-Developed Algorithm
1.8. Boundary-Scan Pattern Configuration Bit Location
1.9. JTAG Instructions
1.10. Sample of Hitless Update Algorithm in Jam Format
1.11. Document Revision History for AN 904: Intel® MAX® 10 Hitless Update Implementation Guidelines
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1.4. Intel® MAX® 10 Hitless Update Requirement and Limitation
The Intel® MAX® 10 hitless update in this guideline must be performed through external JTAG pins. You should use either the Intel® FPGA Download Cable connected to JTAG header or an external host or microprocessor to control the JTAG state machine when running the hitless update flow.
The states of all the output pins are clamped at a user-defined state and no input signal can be read during the clamping period. If you need to process some input signals during the clamping period (from internal configuration complete to clamp release), you can use the global clock pins as input pins in your design. The global clock pins can route the input signals into the core fabric even though the I/Os have not been released.