AN 904: Intel® MAX® 10 Hitless Update Implementation Guidelines

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ID 683380
Date 5/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Hitless Update Implementation Guidelines
1. Intel® MAX® 10 Hitless Update Implementation Guidelines x
1.1. Introduction 1.2. Types of Intel® MAX® 10 Design Update Flow 1.3. Stages of Intel® MAX® 10 Hitless Update Flow 1.4. Intel® MAX® 10 Hitless Update Requirement and Limitation 1.5. Hitless Update using Intel® Quartus® Prime Programmer 1.6. Hitless Update using Intel® Jam STAPL Byte-Code Player 1.7. Hitless Update Using Self-Developed Algorithm 1.8. Boundary-Scan Pattern Configuration Bit Location 1.9. JTAG Instructions 1.10. Sample of Hitless Update Algorithm in Jam Format 1.11. Document Revision History for AN 904: Intel® MAX® 10 Hitless Update Implementation Guidelines
1.5. Hitless Update using Intel® Quartus® Prime Programmer x
1.5.1. Creating IPS File 1.5.2. Executing IPS File
1.6. Hitless Update using Intel® Jam STAPL Byte-Code Player x
1.6.1. Generating .jam/.jbc File 1.6.2. Interpreting Jam File Information using Jam Player
1.7. Hitless Update Using Self-Developed Algorithm x
1.7.1. Custom Algorithm Implementation Flow for Intel® MAX® 10 Devices with SC/SA/SL/DC/DF/DA Feature Options 1.7.2. Custom Algorithm Implementation Flow for Intel® MAX® 10 Devices with DD Feature Option
1. Intel® MAX® 10 Hitless Update Implementation Guidelines

1.10. Sample of Hitless Update Algorithm in Jam Format

The following example shows the Jam Standard Test and Programming Language (STAPL) Format File (.jam) used to execute the hitless update algorithm.

The example below is based on an Intel® MAX® 10 10M50 device. 

ACTION DOWNLOAD = FORCE_REFRESH RECOMMENDED;

DATA DEVICE_DATA;
BOOLEAN sampled[1500]; ‘1500 is the total boundary scan chain bit for 10M50 device
BOOLEAN nstatus_0_confdone_0[1500];
BOOLEAN nstatus_1_confdone_0[1500];
BOOLEAN nstatus_1_confdone_1[1500];
ENDDATA;

PROCEDURE FORCE_REFRESH USES DEVICE_DATA;
'sample all pins state
IRSCAN 	10, $005;
WAIT IDLE, 10 CYCLES, 1 USEC, IDLE;
DRSCAN 1500, $0, CAPTURE sampled[1499..0];
WAIT IDLE, 10 CYCLES, 25 USEC, IDLE;

'MAX10 10M50 boundary scan cell for nSTATUS: Input bit(bit 21) OE bit(bit 22) Output bit (bit 23)
'CONF_DONE: Input bit(bit 12) OE bit(bit 13) Output bit(bit 14)
'Setting nStatus=0, CONF_DONE=0 ... (Pattern A)
nstatus_0_confdone_0[1499..0] = sampled[1499..0];
nstatus_0_confdone_0[12] = 0;
nstatus_0_confdone_0[13] = 0;
nstatus_0_confdone_0[14] = 0;
nstatus_0_confdone_0[21] = 0;
nstatus_0_confdone_0[22] = 0;
nstatus_0_confdone_0[23] = 0;

'Setting nStatus=1, CONF_DONE=0 ... (Pattern B)
nstatus_1_confdone_0[1499..0] = sampled[1499..0];
nstatus_1_confdone_0[12] = 0;
nstatus_1_confdone_0[13] = 0;
nstatus_1_confdone_0[14] = 0;

'Keep nStatus=1, CONF_DONE=1 ... (Pattern C)
nstatus_1_confdone_1[1499..0] = sampled[1499..0];

'Preload sampled pin state with nStatus=0 and CONF_DONE=0 to boundary scan registers
IRSCAN 	10, $005;
WAIT IDLE, 10 CYCLES, 1 USEC, IDLE;
DRSCAN 1500, nstatus_0_confdone_0[1499..0];
WAIT IDLE, 10 CYCLES, 25 USEC, IDLE;

'ISP_ENABLE_CLAMP
IRSCAN	10, $233;	
WAIT 	IDLE, 1000 CYCLES;

'''''User can perform In System Programming here

'ISP_DISABLE
IRSCAN 	10, $201;	
WAIT 	IDLE, 1000 CYCLES;

'EXTEST
IRSCAN	10, $00F;	
WAIT 	IDLE, 1000 CYCLES;

'Preload sampled pin state with nStatus=1 and CONF_DONE=0 to boundary scan registers
DRSCAN 1500, nstatus_1_confdone_0[1499..0];
WAIT IDLE, 10 CYCLES, 25 USEC, IDLE;
WAIT 	IDLE, 1000000 USEC;              

'Preload sampled pin state with nStatus=1 and CONF_DONE=1 to boundary scan registers
DRSCAN 1500, nstatus_1_confdone_1[1499..0];
WAIT IDLE, 10 CYCLES, 25 USEC, IDLE;
WAIT 	IDLE, 4000000 USEC;              'Device already in user mode. User can change any number of delay here before release the I/O  

'TAP reset
STATE 	RESET;                           'I/O release from clamp
ENDPROC;
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