AN 919: Improving Quality of Results with Design Assistant

ID 683369
Date 4/26/2024
Public

Reset Release Intel FPGA IP

Generates a signal to indicate when the device configuration has finished. It is then safe to release reset throughout the device.

Designs can use this IP to gate clocks and write enables or synchronize resets. The Reset Release solves race conditions and spurious writes during power-up. Intel Stratix 10 and Agilex™ 7 devices require one instance of the Reset Release IP in the design. HRR-10204 is run during synthesis and checks that there is exactly one instance of the Reset Release IP in the design.