AN 919: Improving Quality of Results with Design Assistant

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ID 683369
Date 4/26/2024
Public
Document Table of Contents
Document Table of Contents x
Improving Quality of Results with Design Assistant Document Revision History for AN 919: Improving Quality of Results with Design Assistant Appendix A: Running Design Assistant Appendix B: Design Assistant Rules
Improving Quality of Results with Design Assistant x
About Design Assistant About the Design Assistant Design Example Fixing SDC and CDC Rules in the Design Assistant Design Example Fixing Other Faults in the Design Assistant Design Example
Appendix A: Running Design Assistant x
Running Design Assistant
Appendix B: Design Assistant Rules x
Timing Closure Rules Clock Domain Crossing and Reset Domain Crossing Rules Intrinsic Margin Rules Combinatorial Logic Levels Reducing High Fan-out Nets Hyper-Retimer Restrictions Initial Power-Up Conditions Rules Reset Release Intel FPGA IP
Reducing High Fan-out Nets x
Duplication Rules Tension and Span Rules
Initial Power-Up Conditions Rules x
Removing Initial Power-Up Conditions
Improving Quality of Results with Design Assistant
Document Revision History for AN 919: Improving Quality of Results with Design Assistant
Appendix A: Running Design Assistant
Appendix B: Design Assistant Rules

About Design Assistant

Design Assistant conveniently identifies potential design issues, including circuit functionality and timing performance. Identifying and fixing issues early in the design cycle gives fewer and faster iterations. You save time running a full compilation if you solve issues in synthesis or in plan and place fitter stages. Quartus® Prime Pro Edition provides more DRC rules and in more stages. Design Assistant allows the flexibility to choose which rules to run, at what compile stages, and to select and filter rules of interest.
Figure 1. Design Assistant ReportDesign Assistant provides reports in each of the compilation stages when you run it.

Some of the issues that Design Assistant can detect include:

  • Incorrect SDCs
  • Metastability because of clock and reset domain crossings
  • Excessive logic levels
  • High fan-out nets that can cause congestion
  • Potential problems with the design's power-on strategy
  • Retiming Restrictions that prevent the Hyper-Retimer from making optimizations

For faster iterations, run the rules on early-compilation snapshots. For fewer iterations, run lots of rules on the snapshots you have to catch and address all kinds of issues.

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