AN 919: Improving Quality of Results with Design Assistant

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ID 683369
Date 4/26/2024
Public
Document Table of Contents
Document Table of Contents x
Improving Quality of Results with Design Assistant Document Revision History for AN 919: Improving Quality of Results with Design Assistant Appendix A: Running Design Assistant Appendix B: Design Assistant Rules
Improving Quality of Results with Design Assistant x
About Design Assistant About the Design Assistant Design Example Fixing SDC and CDC Rules in the Design Assistant Design Example Fixing Other Faults in the Design Assistant Design Example
Appendix A: Running Design Assistant x
Running Design Assistant
Appendix B: Design Assistant Rules x
Timing Closure Rules Clock Domain Crossing and Reset Domain Crossing Rules Intrinsic Margin Rules Combinatorial Logic Levels Reducing High Fan-out Nets Hyper-Retimer Restrictions Initial Power-Up Conditions Rules Reset Release Intel FPGA IP
Reducing High Fan-out Nets x
Duplication Rules Tension and Span Rules
Initial Power-Up Conditions Rules x
Removing Initial Power-Up Conditions
Improving Quality of Results with Design Assistant
Document Revision History for AN 919: Improving Quality of Results with Design Assistant
Appendix A: Running Design Assistant
Appendix B: Design Assistant Rules

Fixing Other Faults in the Design Assistant Design Example

When you correctly constrain the design and add CDCs, you see fewer rule violations, but the design still needs further optimizations. For this section, refer to the final RTL, which contains many optimizations. Compile the design in the final directory to see the effects of all the changes in this section.
Depending on seed variation, results may differ compared to the screenshots in this section.
  1. Open the design in Quartus® Prime Pro Edition: click File > Open Project and open the top.qpf project file from the intermediate directory.
  2. Under Design Assistant Rule Settings, turn on Enable Design Assistant execution during compilation.
  3. Compile the design.
  4. Analyze the Design Assistant results.
    The report shows fewer rule violations. The missing input delay is on an asynchronous pin and is safe.
    Figure 6. Design Assistant (Signoff) Results
  5. Observe the failing rules during the fitter plan stage. These failing rules point to high fan-out and congestion issues.
    Figure 7. Fitter Plan Stage Failing Rules
  6. Reduce the high fan-out nets in the design (refer to Reducing High Fan-out Nets). Design Assistant can identify high fan-out nets that are candidates for duplication.
    Figure 8. TMC-20601 Registers with High Immediate Fan-out
    Figure 9. TMC-20602 Registers with High Timing Path Endpoint
    1. Divide the memory into stripes to allow for duplication of control signals.
      Figure 10. Memory Control SignalsTMC-20551 identifies some control signals that may need further duplication. It is the write address of a large memory.
    2. Explicitly duplicate registers in the RTL.
    3. Apply the Manual Register Duplication assignments on some of these high fan-out registers.
      Figure 11. Manual Register Duplication Assignments
    4. Duplicate the synchronous reset signal to reduce fan-out.
  7. Observe rule TMC-20204 shows the design setup-failing endpoints with retiming restrictions. Fast-forward compilation can provide recommendations.
    Figure 12. Fast-forward Compilation

    Refer to Hyper-Timing Restrictions for rules that indicate where hyper-retiming is limited. In the design, the timing endpoints are in M20Ks, which is a block that you cannot retime.

    The final RTL removes asynchronous resets and creates a synchronous reset tree. It also adds additional pipeline stages throughout the design including the inputs to memories and on the synchronous reset tree.

  8. Remove initial power-up conditions.
    The design has a signal that didn't reset but controls some other logic, which can lead to functional issues. Refer to the Initial Power-Up Conditions Rules for rules that detect initial conditions in the design.
    RES-30132 detects registers that may not be reset. Review the results to see if design reset the signal and determine if it should be reset.
    Figure 13. RES-30132
    Figure 14. Example of Register to Reset

    Can start at any value and should be reset.

  9. Add a Reset Release IP.
    Figure 15. Reset Release

    The output of the Reset Release IP can gate internal clocks and resets to prevent race conditions. Refer to Reset Release IP for more information. The final RTL includes an instance of the reset release IP.

    Refer to Reset Release IP for more information.
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