11.2. Control

DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

Download PDF

ID 683337

Date 12/04/2023

Version

Public

A newer version of this document is available. Customers should click here to go to the newest version.

Visible to Intel only — GUID: hco1423077006463

Ixiasoft

View Details

11.2. Control

The Control block specifies information about the hardware generation environment and the top-level memory-mapped bus interface widths.

Note: DSP Builder applies globally the options in the Control block to your design.

Note: You must include a Control block in the top-level model.

Table 28. Control Block General Parameters
Parameter	Description
Generate hardware	Turn on to generate output file.
Hardware description language	Specify VHDL or Verilog HDL.
Hardware destination directory	Specify the root directory in which to write the output files. This location can be an absolute path or a relative path (for example, ../rtl). A directory tree is created under this root directory that reflects the names of your model hierarchy.
Use separate working directory for Quartus Prime project	Turn on to create separate working directory.
Generate a single Avalon Conduit interface for the Platform Designer	In v18.1 and earlier, DSP Builder designs that you import and generate in Platform Designer have a single Avalon interface for data, valid, and channel signals. In v19.1 or later, if you regenerate an existing design, turn on (default) this option to preserve the single Avalon Conduit interface. Turn off if you want to connect multiple interfaces in Platform Designer.
Small memory minimum fill	This threshold controls whether the design uses registers or small memories (MLABs) to implement delay lines. DSP Builder uses a small memory only if it fills it with at least the threshold number of bits. On device families that don't support small memories, DSP Builder ignores this threshold.
Medium memory minimum fill	This threshold controls when the design uses a medium memory (M9K, M10K or M20K) instead of a small memory or registers. DSP Builder uses the medium memory only if it fills it with at least the threshold number of bits.
Large memory minimum fill	This threshold controls whether the design uses a large memory (M144K) instead of multiple medium memories. DSP Builder uses the large memory only when it can fill it with at least the threshold number of bits. Default prevents the design using any M144Ks. On device families that don't support large memories, DSP Builder ignores this threshold.
Multiplier: logic and DSP threshold	Specifies the number of logic elements you want to use to save a multiplier. If the estimated cost of implementing a multiplier in logic is no more than this threshold, DSP Builder implements that multiplier in logic. Otherwise DSP Builder uses a hard multiplier. Default means the design always uses hard multipliers. DSP Builder defaults to using DSPs for the multiplications of variable inputs. It uses an internal heuristic to use either a LUT-based or a DSP-based implementation (or a mix of both) if one of the inputs is a constant. This option only applies to the multiplier block, and not to the constant multiplier block.

Table 29. Control Block Clock Parameters
Parameter	Description
Clock signal name	Specifies the name of the system clock signal that DSP Builder uses in the RTL generation, in the _hw.tcl file, and that you see in Platform Designer.
Clock frequency (MHz)	Specifies the system clock rate for the system.
Clock margin (MHz)	Specifies the margin requested to achieve a high system frequency in the fitter. The specified margin does not affect the folding options because the system runs at the rate specified by the Clock frequency parameter setting. Specify a positive clock margin if you need to pipeline your design more aggressively (or specify a negative clock margin to save resources) when you do not want to change the ratio between the clock speed and the bus speed.
Reset signal name	Specifies the name of the reset signal that DSP Builder uses in the RTL generation, the _hw.tcl file, and that you see in Platform Designer.
Reset active	Specifies whether the logic generated is reset with an active high or active low reset signal.
Use default minimum reset pulse width	Turn on to enter a minimum reset value pulse width.
Minimum reset pulse width	Enter a value for the minimum number of system clock cycles for which you assert the reset signal in your target hardware. This setting does not enforce that your design correctly resets in the number of cycles you specify, in particular when you apply reset minimization. You should simulate your design with this value (which DSP Builder applies in the simulation testbench) to confirm that your design works. DSP Builder reset minimization uses a longer minimum reset pulse width to remove resets on the control path. Applying a reset value at an earlier register propagates to later registers during the reset period, without them needing an explicit reset. When you turn Global enable On, DSP Builder enters a large, minimum reset pulse width according to the reset-minimization. When you turn Global enable Off it selects a small minimum reset pulse width as in previous versions of DSP Builder. DSP Builder reports the actual minimum reset pulse width value when it generates your design.

Table 30. Control Block Testbenches Tab Parameters
Parameter	Description
Create automatic testbenches	Turn on to generate additional automatic testbench files. These files capture the input and output of each block in a .stm file. DSP Builder creates a test harness (_atb.vhd) that simulates the generated RTL alongside the captured data. DSP Builder generates a script ( `<model>`_atb.do) that you can use to simulate the design in ModelSim and ensure bit and cycle accuracy between the Simulink model and the generated RTL.
Action on ChannelOut mismatch	Select Error or Warning.
Import ModelSim results to MATLAB	Turn on to import the ModelSim simulator results back into MATLAB. Specify: The name of the variable to which you assign the device output The name of the variable to which you assign the valid map The name of the function to process the results.
Floating-point mismatch tolerance	Specify the floating-point mismatch tolerance, which is the largest difference in magnitude for a signal value to be equivalent. Use this field to record cumulative differences in floating-point precision between the Simulink model and the RTL.
Floating-point zero mismatch tolerance	Specify the floating-point mismatch zero tolerance, which is the largest magnitude for a signal value to be equivalent to zero. Use this field to record cumulative differences in floating point precision between the Simulink model and the RTL.
ModelSim input values during reset	Defines the behavior of ModelSim input signals during the period in which DSP Builder holds your design in reset. Use this parameter to test whether the values of the input data during reset affect the behavior of a design with reset-minimization. The Simulink simulation assumes all inputs are zero during reset. Using a non-zero value causes a mismatch if input values during reset affect the RTL behavior. To eliminate this behavior, place a mux on the inputs, which sets them to zero during reset. Only valid if the Minimum reset pulse width is greater than 1 clock cycle. This parameter can be: 0, (default) holds all input data at zero during reset. This matches the Simulink simulation and does not identify any RTL dependence on input values during reset. 1, sets all bits of all input data to 1. X, sets all bits of all input data to X. 01, alternates all bits of all input data between 0 and 1 on each clock cycle. X01, alternates all bits of all input data between X, 0 and 1 on each clock cycle.

Table 31. Optimization Tab ParametersSets the reset minimization parameters, which default to Auto. When set to Auto, DSP Builder turns on Global enable and Floating-point, if the design targets a HyperFlex device.
Parameter	Value	Description
Reset - Minimization
Global enable	Auto, on, or off	Globally enables reset minimization. DSP Builder also applies local settings on the SynthesisInfo blocks. Reset minimization applies to all subsystems in your design that include ChannelIn and ChannelOut blocks. DSP Builder does not apply reset minimization to subsystems that include GPIn and GPOut blocks. When global enable is on, use the SynthesisInfo block to change its behavior at the subsystem level.
Floating-point	Auto, on, or off	Applies reset minimization to all floating-point operators. Use this feature when your design employs floating-point operators that are not control flow.
Uninitialized Memory Content
Uninitialized means	0 - Initialized to Zeroes or X - Truly Uninitialized	Specify what happens when you turn off Initialize Hardware Memory Blocks with Initial Data Contents on any memory block (DualMem or SharedMem) in your design. This parameter does not apply to your memory blocks when you turn on Initialize Hardware Memory Blocks with Initial Data Contents for a memory block. 0 - Initialized to Zeroes means the content of each uninitialized memory is zeroes in: Simulink simulation HDL simulation Hardware X - Truly Uninitialized means the content of each uninitialized memory is: Zeroes in Simulink simulation Xs in HDL simulation Undefined in hardware. DSP Builder cannot represent undefined or X initial values it reads from the memory in Simulink simulation. Unless you eliminate such values with suitable logic, you may see a mismatch in HDL simulation. The default value is 0 - Initialized to Zeroes, which is benign in simulation.
FIFO Optimizations
Report FIFO fill level	-	Turn on to report the maximum FIFO depth reached during simulation to the Simulink Diagnostic Viewer. You can use the information to optimize the FIFO buffers.

Table 32. **Simulation Tab**
Parameter	Description
Simulation Mode	Select the simulation mode that applies to primitive subsystems where you configure the Simulation mode to be Use Global Value in the SynthesisInfo block. The options are: Standard. A block-level simulation model that provides the fastest simulation with mathematical numerical accuracy. The default option. Bit Accurate. A bit-accurate simulation model that more closely models the hardware, particularly for floating-point designs. The bit-accurate model models algorithmic delay but does not model latency balancing delay within the datapath. Instead, to approximate cycle-accuracy, DSP Builder applies a latency correction to the outputs. Scope values inside primitive subsystems may not be accurate when using this model, because the scope values are obtained from the Standard simulation, which runs in parallel to the bit-accurate model. Bit and Cycle Accurate. As for Bit Accurate but with cycle accuracy within the datapath. However, as for Bit Accurate, scope values may still not be accurate.
Bus simulation mode	Select a trade-off between simulation speed and simulation accuracy for primitive subsystems that make use of Memory Mapped library blocks: Register Bit, Register Field, Register Out, and Shared Memory. Standard. A simplified block-level simulation model that provides the fastest simulation but lacks timing fidelity. Changes in bus stimulus may not occur at the same time as in hardware simulation. The timing may be incorrect by as much as the total latency of the subsystem. Bit and Cycle Accurate. A bit-accurate simulation model that provides cycle accurate timing fidelity of the underlying bus fabric. Does not support designs with a separate bus clock.
C++ Software Model Generation	Refer to Software Model Options

Options in the Control block specify whether hardware generates for your design example and the location of the generated RTL. You can also create automatic RTL testbenches for each subsystem in your design example and specify the depth of signals that DSP Builder includes when your design example simulates in the ModelSim simulator.

You can specify the address and data bus widths that the memory-mapped bus interface use and specify whether DSP Builder stores the high-order byte of the address in memory at the lowest address and the low-order byte at the highest address (big endian), or the high-order byte at the highest address and the low-order byte at the lowest address (little endian).

Select Your Language

Using Intel.com Search

Quick Links

Recent Searches

Advanced Search

Only search in

DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

11.2. Control