Intel® Arria® 10 GX/GT Device Errata and Design Recommendations

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ID 683331
Date 8/03/2022
Public
Document Table of Contents
Document Table of Contents x
1. About this Document
1. About this Document x
1.1. Design Recommendations for Intel® Arria® 10 GX/GT Devices 1.2. Device Errata for Intel® Arria® 10 GX/GT Devices 1.3. Document Revision History for Intel® Arria® 10 GX/GT Device Errata and Design Recommendations
1.1. Design Recommendations for Intel® Arria® 10 GX/GT Devices x
1.1.1. Intel® Arria® 10 Device Lifetime Guidance
1.1.1. Intel® Arria® 10 Device Lifetime Guidance x
1.1.1.1. Design Recommendation
1.2. Device Errata for Intel® Arria® 10 GX/GT Devices x
1.2.1. Automatic Lane Polarity Inversion for PCIe Hard IP 1.2.2. Link Equalization Request Bit in the PCIe Hard IP Cannot Be Cleared by Software 1.2.3. High VCCBAT Current when VCC is Powered Down 1.2.4. Failure on Row Y59 When Using the Error Detection Cyclic Redundancy Check (EDCRC) or Partial Reconfiguration (PR) 1.2.5. GPIO Output may not meet the On-Chip Series Termination (Rs OCT) without Calibration Resistance Tolerance Specification or Current Strength Expectation
1. About this Document

1.2.2. Link Equalization Request Bit in the PCIe Hard IP Cannot Be Cleared by Software

Link Equalization Request bit of the PCIe Hard IP

The Link Equalization Request bit (bit 5 of the Link Status 2 Register) is set during PCIe Gen3 link equalization. Once set, this bit cannot be cleared by software. The autonomous equalization mechanism is not affected by this issue, but the software equalization mechanism may be impacted depending on the usage of the Link Equalization Request bit.

Workaround

Avoid using software-based link equalization mechanism for both PCIe endpoint and root port implementations.

Status

Affects: Intel® Arria® 10 GX/GT devices.

Status: No planned fix.

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