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Ixiasoft
1.2.1. Automatic Lane Polarity Inversion for PCIe Hard IP
1.2.2. Link Equalization Request Bit in the PCIe Hard IP Cannot Be Cleared by Software
1.2.3. High VCCBAT Current when VCC is Powered Down
1.2.4. Failure on Row Y59 When Using the Error Detection Cyclic Redundancy Check (EDCRC) or Partial Reconfiguration (PR)
1.2.5. GPIO Output may not meet the On-Chip Series Termination (Rs OCT) without Calibration Resistance Tolerance Specification or Current Strength Expectation
Visible to Intel only — GUID: pya1493871560356
Ixiasoft
1.1.1. Intel® Arria® 10 Device Lifetime Guidance
The table below describes the Intel® Arria® 10 product family lifetime guidance corresponding to VGA gain settings.
VGA Gain Setting | Device Lifetime Guidance for Continuous Operation 1 | |
---|---|---|
100°C TJ (Years) | 90°C TJ (Years) | |
0 | 11.4 | 11.4 |
1 | 11.4 | 11.4 |
2 | 11.4 | 11.4 |
3 | 11.4 | 11.4 |
4 | 11.4 | 11.4 |
5 | 9.3 | 11.4 |
6 | 6.9 | 11.4 |
7 | 5.4 | 11.4 |
1 Device lifetime recommendation calculation assumes the device is configured and the transceiver is always powered up (24 x 7 x 365).