Visible to Intel only — GUID: cqs1493873226438
Ixiasoft
1.2.1. Automatic Lane Polarity Inversion for PCIe Hard IP
1.2.2. Link Equalization Request Bit in the PCIe Hard IP Cannot Be Cleared by Software
1.2.3. High VCCBAT Current when VCC is Powered Down
1.2.4. Failure on Row Y59 When Using the Error Detection Cyclic Redundancy Check (EDCRC) or Partial Reconfiguration (PR)
1.2.5. GPIO Output may not meet the On-Chip Series Termination (Rs OCT) without Calibration Resistance Tolerance Specification or Current Strength Expectation
Visible to Intel only — GUID: cqs1493873226438
Ixiasoft
1.3. Document Revision History for Intel® Arria® 10 GX/GT Device Errata and Design Recommendations
Document Version | Changes |
---|---|
2022.08.03 | Added a new erratum: GPIO Output may not meet the On-Chip Series Termination (Rs OCT) without Calibration Resistance Tolerance Specification or Current Strength Expectation. |
2020.01.10 | Added a new erratum: Failure on Row Y59 When Using the Error Detection Cyclic Redundancy Check (EDCRC) or Partial Reconfiguration (PR). |
2019.12.23 | Added a new erratum: Link Equalization Request Bit in the PCIe Hard IP Cannot Be Cleared by Software. |
2017.12.20 | Added a new erratum: High VCCBAT Current when VCC is Powered Down. |
2017.07.28 | Initial release. |