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Ixiasoft
1.2.1. Automatic Lane Polarity Inversion for PCIe Hard IP
1.2.2. Link Equalization Request Bit in the PCIe Hard IP Cannot Be Cleared by Software
1.2.3. High VCCBAT Current when VCC is Powered Down
1.2.4. Failure on Row Y59 When Using the Error Detection Cyclic Redundancy Check (EDCRC) or Partial Reconfiguration (PR)
1.2.5. GPIO Output may not meet the On-Chip Series Termination (Rs OCT) without Calibration Resistance Tolerance Specification or Current Strength Expectation
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Ixiasoft
1.1.1.1. Design Recommendation
If you are using VGA gain settings of 5, 6, or 7 and require an 11.4-year lifetime, Intel recommends either one of the following guidelines:
- Change the VGA gain setting to 4, and re-tune the link, or
- Limit the junction temperature TJ to 90°C.