Intel® Arria® 10 GX/GT Device Errata and Design Recommendations

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ID 683331
Date 8/03/2022
Public
Document Table of Contents
Document Table of Contents x
1. About this Document
1. About this Document x
1.1. Design Recommendations for Intel® Arria® 10 GX/GT Devices 1.2. Device Errata for Intel® Arria® 10 GX/GT Devices 1.3. Document Revision History for Intel® Arria® 10 GX/GT Device Errata and Design Recommendations
1.1. Design Recommendations for Intel® Arria® 10 GX/GT Devices x
1.1.1. Intel® Arria® 10 Device Lifetime Guidance
1.1.1. Intel® Arria® 10 Device Lifetime Guidance x
1.1.1.1. Design Recommendation
1.2. Device Errata for Intel® Arria® 10 GX/GT Devices x
1.2.1. Automatic Lane Polarity Inversion for PCIe Hard IP 1.2.2. Link Equalization Request Bit in the PCIe Hard IP Cannot Be Cleared by Software 1.2.3. High VCCBAT Current when VCC is Powered Down 1.2.4. Failure on Row Y59 When Using the Error Detection Cyclic Redundancy Check (EDCRC) or Partial Reconfiguration (PR) Workaround Status 1.2.5. GPIO Output may not meet the On-Chip Series Termination (Rs OCT) without Calibration Resistance Tolerance Specification or Current Strength Expectation
1. About this Document

1.2.4. Failure on Row Y59 When Using the Error Detection Cyclic Redundancy Check (EDCRC) or Partial Reconfiguration (PR)

When the error detection cyclic redundancy check (EDCRC) or partial reconfiguration (PR) feature is enabled, you may encounter unexpected output from clocked components such as flip-flop or DSP or M20K or LUTRAM that are placed at row 59 in Intel® Arria® 10 GX devices.

This failure is sensitive to temperature and voltage.

Intel® Quartus® Prime software version 18.1.1 and later displays the following error message:
  • In Intel® Quartus® Prime Standard Edition:
    • Info (20411): EDCRC usage detected. To ensure reliable operation of these features on the targeted device, certain device resources must be disabled.
    • Error (20412): You must create a floorplan assignment to block out the device resources at row Y=59 and ensure reliable operation with EDCRC. Use the Logic Lock (Standard) Regions Window to create an empty reserved region with origin X0_Y59, height = 1 and width = <#>. Also, review any existing Logic Lock (Standard) regions that overlap that row and ensure if they account for the unused device resources.
  • In Intel® Quartus® Prime Pro Edition:
    • Info (20411): PR and/or EDCRC usage detected. To ensure reliable operation of these features on the targeted device, certain device resources must be disabled.
    • Error (20412): You must create a floorplan assignment to block out the device resources at row Y=59 and ensure reliable operation with PR and/or EDCRC. Use the Logic Lock Regions Window to create an empty reserved region, or add set_instance_assignment -name EMPTY_PLACE_REGION "X0 Y59 X<#> Y59-R:C-empty_region" -to | directly to your Quartus Settings File (.qsf). Also, review any existing Logic Lock regions that overlap that row and ensure if they account for the unused device resources.
Note: Intel® Quartus® Prime software versions 18.1 and earlier do not report these errors.

Workaround

Apply the empty logic lock region instance in the Quartus Prime Settings File (.qsf) to avoid use of row Y59. For more information, refer to the corresponding knowledge base.

Status

Affects:
  • Intel® Arria® 10 GX 160 devices
  • Intel® Arria® 10 GX 220 devices
  • Intel® Arria® 10 GX 270 devices
  • Intel® Arria® 10 GX 320 devices

Status: No planned fix.

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