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1. Serial Lite III Streaming Intel® FPGA IP Quick Reference
2. About the Serial Lite III Streaming Intel® FPGA IP
3. Getting Started
4. Serial Lite III Streaming IP Core Design Examples
5. Serial Lite III Streaming Intel® FPGA IP Functional Description
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines
9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Intel® FPGA IP Evaluation Mode
3.3. Specifying IP Core Parameters and Options
3.4. Serial Lite III Streaming Intel® FPGA IP Parameters
3.5. Transceiver Reconfiguration Controller for Stratix® V and Arria® V GZ Designs
3.6. IP Generation Output ( Quartus® Prime Pro Edition)
3.7. IP Core Generation Output ( Quartus® Prime Standard Edition)
3.8. Simulating
5.1. IP Architecture
5.2. Transmission Overheads and Lane Rate Calculations
5.3. Reset
5.4. Link-Up Sequence
5.5. Error Detection, Reporting, and Recovering Mechanism
5.6. CRC-32 Error Injection
5.7. FIFO ECC Protection
5.8. User Data Interface Waveforms
5.9. Signals
5.10. Accessing Configuration and Status Registers
5.1.1. Serial Lite III Streaming Source Core
5.1.2. Serial Lite III Streaming Sink Core
5.1.3. Serial Lite III Streaming IP Core Duplex Core
5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode
5.1.5. Stratix® 10, Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V GZ Variations
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5.8. User Data Interface Waveforms
The following waveforms apply to the Serial Lite III Streaming IP core source user interface in source-only and duplex cores.
Figure 11. Source Waveform for Burst Mode
Figure 12. Source Waveform for Burst Mode (Sync)
Figure 13. Source Waveform for Continuous Mode
- start_of_burst pulses for one clock cycle, indicating that the data burst starts at that clock cycle.
- end_of_burst pulses for one clock cycle, indicating that the data burst ends at that clock cycle.
- The valid signal indicates valid data. It should be turned off between two data bursts that are between the current data burst's end_of_burst clock cycle and next data burst's start_of_burst clock cycle. The valid signal can be pulled low in the middle of a data burst transferring between the same data burst's start_of_burst and end_of_burst, indicating non-valid data at that clock cycle.
- The sync vector is used in burst mode. It is valid only when start_of_burst and valid are high. Multiple logical channel is time-multiplexed into physical channels. Sync vector can be used to store the logical channel number that the burst targets. The logical channel number is multiplexed into the sync vector during the start_of_burst. The value is embedded into the data and sent over to the receiving party. The sink can extract the channel number from start_of_burst data bus to output on the sync vector of the sink. The sync vector can also be used to include empty information which indicates invalid data at the end_of_burst. In this case, the empty value is multiplexed into the sync vector during end_of_burst. The data is again embedded inside and sent over to the receiving party. The sink extracts the information and output on the sync vector of the sink.
The following waveforms apply to the sink user interface in sink-only and duplex cores.
Figure 14. Sink Waveform for Burst Mode
Figure 15. Sink Waveform for Continuous Mode
- start_of_burst pulses for one clock cycle, indicating that the data burst starts at that clock cycle.
- end_of_burst pulses for one clock cycle, indicating that the data burst ends at that clock cycle.
- The valid signal indicates valid data. It is turned off between two data bursts that are between the current data burst's end_of_burst clock cycle and the next data burst's start_of_burst clock cycle. The valid signal can be pulled low in the middle of a data burst after a data burst's start_of_burst and before the data burst's end_of_burst, indicating non-valid data at that clock cycle.
- The sync vector is used in burst mode. The sync data picked up at the source's start_of_burst high cycle is sent out at the sink as shown in the waveform. Multiple logical channel is time-multiplexed into physical channels. Sync vector can be used to store the logical channel number that the burst targets. The logical channel number is multiplexed into the sync vector during the start_of_burst. The value is embedded into the data and sent over to the receiving party. The sink can extract the channel number from start_of_burst data bus to output on the sync vector of the sink. The sync vector can also be used to include empty information which indicates invalid data at the end_of_burst. In this case, the empty value is multiplexed into the sync vector during end_of_burst. The data is again embedded inside and sent over to the receiving party. The sink extracts the information and output on the sync vector of the sink.