Serial Lite III Streaming Intel® FPGA IP User Guide

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ID 683330
Date 5/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference 2. About the Serial Lite III Streaming Intel® FPGA IP 3. Getting Started 4. Serial Lite III Streaming IP Core Design Examples 5. Serial Lite III Streaming Intel® FPGA IP Functional Description 6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines 7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers 8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines 9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives 10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide
2. About the Serial Lite III Streaming Intel® FPGA IP x
2.1. Serial Lite III Streaming Intel® FPGA IP Protocol 2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes 2.3. Performance and Resource Utilization
2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes x
2.2.1. Continuous Mode 2.2.2. Burst Mode
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Intel® FPGA IP Evaluation Mode 3.3. Specifying IP Core Parameters and Options 3.4. Serial Lite III Streaming Intel® FPGA IP Parameters 3.5. Transceiver Reconfiguration Controller for Stratix® V and Arria® V GZ Designs 3.6. IP Generation Output ( Quartus® Prime Pro Edition) 3.7. IP Core Generation Output ( Quartus® Prime Standard Edition) 3.8. Simulating
3.2. Intel® FPGA IP Evaluation Mode x
3.2.1. Intel® FPGA IP Evaluation Mode Timeout Behavior
3.3. Specifying IP Core Parameters and Options x
3.3.1. Serial Lite III Streaming Intel® FPGA IP Parameter Editor 3.3.2. Arria® 10 and Cyclone® 10 GX Designs
3.4. Serial Lite III Streaming Intel® FPGA IP Parameters x
3.4.1. Parameters 3.4.2. Parameter Settings for Stratix® 10 Devices 3.4.3. Parameter Settings for Arria® 10 and Cyclone® 10 GX Devices 3.4.4. Parameter Settings for Stratix V and Arria V GZ Devices
3.8. Simulating x
3.8.1. Simulating Intel® FPGA IP Cores 3.8.2. Simulation Parameters 3.8.3. Simulating and Verifying the Design
4. Serial Lite III Streaming IP Core Design Examples x
4.1. Serial Lite III Streaming IP Core Design Example for Stratix® 10 Devices 4.2. Serial Lite III Streaming IP Core Design Example for Arria® 10 and Cyclone® 10 GX Devices 4.3. Serial Lite III Streaming IP Design Examples for Stratix® V Devices
5. Serial Lite III Streaming Intel® FPGA IP Functional Description x
5.1. IP Architecture 5.2. Transmission Overheads and Lane Rate Calculations 5.3. Reset 5.4. Link-Up Sequence 5.5. Error Detection, Reporting, and Recovering Mechanism 5.6. CRC-32 Error Injection 5.7. FIFO ECC Protection 5.8. User Data Interface Waveforms 5.9. Signals 5.10. Accessing Configuration and Status Registers
5.1. IP Architecture x
5.1.1. Serial Lite III Streaming Source Core 5.1.2. Serial Lite III Streaming Sink Core 5.1.3. Serial Lite III Streaming IP Core Duplex Core 5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode 5.1.5. Stratix® 10, Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V GZ Variations
5.1.1. Serial Lite III Streaming Source Core x
5.1.1.1. Source Application Module 5.1.1.2. Source Adaptation Module 5.1.1.3. Interlaken PHY IP TX Core or Native PHY IP TX Core - Interlaken Mode 5.1.1.4. Source Clock Generator
5.1.2. Serial Lite III Streaming Sink Core x
5.1.2.1. Sink Application Module 5.1.2.2. Sink Adaptation Module 5.1.2.3. Lane Alignment Module 5.1.2.4. Interlaken PHY IP RX Core or Native PHY IP RX Core - Interlaken Mode 5.1.2.5. Sink Clock Generator
5.9. Signals x
5.9.1. Serial Lite III Streaming Intel® FPGA IP Interface Signals 5.9.2. Signals for Stratix® 10 Devices 5.9.3. Signals for Arria® 10 and Cyclone® 10 GX Devices 5.9.4. Signals for Stratix® V and Arria® V GZ Devices
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines x
6.1. Standard Clocking Mode 6.2. Advanced Clocking Mode 6.3. Standard Clocking Mode vs Advanced Clocking Mode 6.4. Clocking Implementation Guidelines 6.5. Core Latency
6.1. Standard Clocking Mode x
6.1.1. Standard Clocking Mode in Serial Lite III Streaming Intel® FPGA IP Core ( Stratix® 10 Devices) 6.1.2. Standard Clocking Mode in Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Devices Example of Implementing Specific User Interface Clock Frequency
6.2. Advanced Clocking Mode x
6.2.1. Advanced Clocking Mode Structure for Serial Lite III Streaming Intel FPGA IP Core ( Stratix® 10 Devices) 6.2.2. Advanced Clocking Mode Structure For Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.4. Clocking Implementation Guidelines x
6.4.1. Choosing TX PLL Type
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers x
7.1. Register Map 7.2. Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines x
8.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy 8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging
8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging x
8.2.1. Source Core Link Debugging 8.2.2. Sink Core Link Debugging
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference
2. About the Serial Lite III Streaming Intel® FPGA IP
3. Getting Started
4. Serial Lite III Streaming IP Core Design Examples
5. Serial Lite III Streaming Intel® FPGA IP Functional Description
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines
9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide

6.1.2. Standard Clocking Mode in Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Devices

The standard clocking mode is an implementation with no PPM differences in IP core. In this mode, you initially specify the user clock frequency through the parameter editor. The Quartus® Prime software then automatically determines the required reference clock coming from the Transceiver Native PHY for Arria® 10 and Cyclone® 10 GX devices or Interlaken PHY for Stratix® V and Arria® V devices, and the two clock outputs from the fPLL in the clock generator module.

After the calculation, the Quartus® Prime software provides a list of transceiver reference clock values for you to select. It also shows the user clock value in the parameter editor. The Serial Lite III Streaming IP core generates the user clock output for source and sink user interfaces with value identical to the user clock frequency that you specify depending on the clock constraints.

Figures below shows the source and sink variant clocking structure for standard clocking mode in Arria® 10 and Cyclone® 10 GX devices.
Figure 18. Standard Clocking Mode Structure for Arria® 10 and Cyclone® 10 GX Devices
Figure 19. Standard Clocking Mode Structure for Stratix V or Arria V Devices
Table 37.   Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Clocks in Standard Clocking Mode
Clock Name Description
Source
user_clock User-defined. This clock is determined by the required throughput of the user application. For example, if the user interface is 384-bits wide (6 lanes × 64 bit/lane) and the required throughput is 120 Gbps, the user_clock frequency is 312.5 MHz. This is an output clock provided by the IP core to the user. This clock should be used to clock the user interface.
tx_serial_clk ( Arria® 10 and Cyclone® 10 GX devices) This clock should toggle at one-half the data rate of the transceiver lane. When you enter the user_clock frequency in the IP parameter editor, the per lane data rate is calculated. Use that value and divided it by two to determine the tx_serial_clk. You are required to instantiate the TX PLL, as shown in the figure above. An example of the TX PLL (ATX PLL) is generated with the IP core and is configured with the required reference clock and tx_serial_clk.
tx_pll_ref_clk ( Stratix® V and Arria® V devices) This is the reference clock for the transceiver TX PLL. The frequency is selected from the available values in the IP parameter editor and must match that value.
tx_clkout This clock is not exposed to the user. It is used as a reference clock for the internal PLL. The frequency of tx_clkout is the data rate divided by 64.
interface_clock This clock is an internal clock and is not exposed to the user. The frequency of this clock is calculated by the IP parameter editor and is the transceiver data rate divided by transceiver PCS-PMA width (64 bits). The internal PLL is configured to generate the required frequency.
Sink
user_clock User-defined. This clock is determined by the required throughput of the user application. For example, if the user interface is 384-bits wide (6 lanes × 64 bit/lane) and the required throughput is 120 Gbps, the user_clock frequency is 312.5 MHz. The frequency of this clock should match the frequency of the user_clock in the Source variant. This is an output clock provided by the IP core to the user. This clock should be used to clock the RX user application that drives the RX user interface.
xcvr_pll_ref_clk This reference clock is used by the Clock Data Recovery (CDR) unit in the transceiver. It serves as a reference for the CDR to recover the clock from the serial line. The frequency of this clock must match the frequency you select in the IP parameter editor. It should also match the frequency of the tx_pll_ref_clk reference clock for the TX PLL at the Source variant.
rx_clkout This clock is not exposed to the user. It is used as a reference clock for the internal PLL in the Sink. The frequency of rx_clkout is the data rate divided by 64.
interface_clock This clock is an internal clock and is not exposed to the user. The frequency of this clock is calculated by the IP parameter editor and is the transceiver data rate divided by transceiver PCS-PMA width (64 bits). The internal PLL is configured to generate the required frequency.

Example of Implementing Specific User Interface Clock Frequency

An application requires the Serial Lite III Streaming Arria® 10 FPGA IP core to sustain a frequency of 300 Gbps at the user interface.

user_clock (frequency) × number_of_lanes × 64 bits/lane = 300 Gbps

The data rate for Arria® 10 GX transceivers is limited to 17.4 Gbps. Therefore, 300 Gbps / 17.4 Gbps = 18 (rounding up)

Choosing 18 lanes gives:

user_clock (frequency) = 300 / (18 × 64) = 260.42 MHz

A value of 260.40 MHz is out of the supported range for the user_clock frequency. Therefore, you need to add one more lane.

user_clock (frequency) = 300 / (19 × 64) = 246.71 MHz

Choosing 246.71 MHz as the user_clock, the IP core provides the following values:

Transceiver data rate: 17.368 Gbps

tx_clkout: 17.368 / 64 = 271.375 MHz

interface_clk: 17.368 / 64 = 271.375 MHz

tx_serial_clock: 17.368 / 2 = 8684 MHz

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