Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 5/23/2024
Public
Document Table of Contents

8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging

The following section describes the link-up sequence that you can use when debugging the Serial Lite III Streaming Intel® FPGA IP. The internal signals in the charts and tables can be observed by the Signal Tap.