Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 5/23/2024
Public
Document Table of Contents

5.1. IP Architecture

The Serial Lite III Streaming Intel® FPGA IP has three variations:

  • Source (simplex transmitter)—formats streaming data from the user application and transmits the data over serial links.
  • Sink (simplex receiver)—receives the serial stream data from serial links, removes any formatting information, and delivers the data to the user application.
  • Duplex (transmitter and receiver)—composed of both the source and sink cores. The streaming data can be transmitted and received in both directions.

All three variations include the L-Tile/H-Tile Transceiver Native PHY Stratix® 10 FPGA IP in Interlaken mode for Stratix® 10 devices, Transceiver Native PHY IP for Arria® 10 and Cyclone® 10 GX devices in Interlaken mode, or Interlaken PHY v18.1 IP for Stratix® V and Arria® V GZ devices that utilizes hardened PCS and PMA modules. Source only and sink only variants are not available if you select E-Tile as the transceiver. The source and sink cores use the Transceiver Native PHY or Interlaken PHY v18.1 IPs in simplex mode, and the duplex core uses the Transceiver Native PHY or Interlaken PHY v18.1 IP in duplex mode.

Table 20.  IP and Functions
Source Core Sink Core
  • Data encapsulation
  • Generation and insertion of Idle Control Words
  • Lane striping for multi-lane link
  • User synchronization and burst marker insertion
  • Multi-lane alignment
  • Data decapsulation
  • Idle Control Words removal
  • Lane de-striping
  • User synchronization and burst marker demultiplexing
Figure 7.  Serial Lite III Streaming IP core with Source and Sink Cores
Figure 8.  Serial Lite III Streaming IP Core Duplex Core