Serial Lite III Streaming Intel® FPGA IP User Guide

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ID 683330
Date 5/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference 2. About the Serial Lite III Streaming Intel® FPGA IP 3. Getting Started 4. Serial Lite III Streaming IP Core Design Examples 5. Serial Lite III Streaming Intel® FPGA IP Functional Description 6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines 7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers 8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines 9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives 10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide
2. About the Serial Lite III Streaming Intel® FPGA IP x
2.1. Serial Lite III Streaming Intel® FPGA IP Protocol 2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes 2.3. Performance and Resource Utilization
2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes x
2.2.1. Continuous Mode 2.2.2. Burst Mode
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Intel® FPGA IP Evaluation Mode 3.3. Specifying IP Core Parameters and Options 3.4. Serial Lite III Streaming Intel® FPGA IP Parameters 3.5. Transceiver Reconfiguration Controller for Stratix® V and Arria® V GZ Designs 3.6. IP Generation Output ( Quartus® Prime Pro Edition) 3.7. IP Core Generation Output ( Quartus® Prime Standard Edition) 3.8. Simulating
3.2. Intel® FPGA IP Evaluation Mode x
3.2.1. Intel® FPGA IP Evaluation Mode Timeout Behavior
3.3. Specifying IP Core Parameters and Options x
3.3.1. Serial Lite III Streaming Intel® FPGA IP Parameter Editor 3.3.2. Arria® 10 and Cyclone® 10 GX Designs
3.4. Serial Lite III Streaming Intel® FPGA IP Parameters x
3.4.1. Parameters 3.4.2. Parameter Settings for Stratix® 10 Devices 3.4.3. Parameter Settings for Arria® 10 and Cyclone® 10 GX Devices 3.4.4. Parameter Settings for Stratix V and Arria V GZ Devices
3.8. Simulating x
3.8.1. Simulating Intel® FPGA IP Cores 3.8.2. Simulation Parameters 3.8.3. Simulating and Verifying the Design
4. Serial Lite III Streaming IP Core Design Examples x
4.1. Serial Lite III Streaming IP Core Design Example for Stratix® 10 Devices 4.2. Serial Lite III Streaming IP Core Design Example for Arria® 10 and Cyclone® 10 GX Devices 4.3. Serial Lite III Streaming IP Design Examples for Stratix® V Devices
5. Serial Lite III Streaming Intel® FPGA IP Functional Description x
5.1. IP Architecture 5.2. Transmission Overheads and Lane Rate Calculations 5.3. Reset 5.4. Link-Up Sequence 5.5. Error Detection, Reporting, and Recovering Mechanism 5.6. CRC-32 Error Injection 5.7. FIFO ECC Protection 5.8. User Data Interface Waveforms 5.9. Signals 5.10. Accessing Configuration and Status Registers
5.1. IP Architecture x
5.1.1. Serial Lite III Streaming Source Core 5.1.2. Serial Lite III Streaming Sink Core 5.1.3. Serial Lite III Streaming IP Core Duplex Core 5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode 5.1.5. Stratix® 10, Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V GZ Variations
5.1.1. Serial Lite III Streaming Source Core x
5.1.1.1. Source Application Module 5.1.1.2. Source Adaptation Module 5.1.1.3. Interlaken PHY IP TX Core or Native PHY IP TX Core - Interlaken Mode 5.1.1.4. Source Clock Generator
5.1.2. Serial Lite III Streaming Sink Core x
5.1.2.1. Sink Application Module 5.1.2.2. Sink Adaptation Module 5.1.2.3. Lane Alignment Module 5.1.2.4. Interlaken PHY IP RX Core or Native PHY IP RX Core - Interlaken Mode 5.1.2.5. Sink Clock Generator
5.9. Signals x
5.9.1. Serial Lite III Streaming Intel® FPGA IP Interface Signals 5.9.2. Signals for Stratix® 10 Devices 5.9.3. Signals for Arria® 10 and Cyclone® 10 GX Devices 5.9.4. Signals for Stratix® V and Arria® V GZ Devices
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines x
6.1. Standard Clocking Mode 6.2. Advanced Clocking Mode 6.3. Standard Clocking Mode vs Advanced Clocking Mode 6.4. Clocking Implementation Guidelines 6.5. Core Latency
6.1. Standard Clocking Mode x
6.1.1. Standard Clocking Mode in Serial Lite III Streaming Intel® FPGA IP Core ( Stratix® 10 Devices) 6.1.2. Standard Clocking Mode in Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.2. Advanced Clocking Mode x
6.2.1. Advanced Clocking Mode Structure for Serial Lite III Streaming Intel FPGA IP Core ( Stratix® 10 Devices) 6.2.2. Advanced Clocking Mode Structure For Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.4. Clocking Implementation Guidelines x
6.4.1. Choosing TX PLL Type
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers x
7.1. Register Map 7.2. Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines x
8.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy 8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging
8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging x
8.2.1. Source Core Link Debugging 8.2.2. Sink Core Link Debugging
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference
2. About the Serial Lite III Streaming Intel® FPGA IP
3. Getting Started
4. Serial Lite III Streaming IP Core Design Examples
5. Serial Lite III Streaming Intel® FPGA IP Functional Description
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines
9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide

5.5. Error Detection, Reporting, and Recovering Mechanism

Table 23.  Error Conditions, Core Behavior, Reporting, and Recovering MechanismThis table lists the error conditions that the core detect, their behavior in response to each condition, and available reporting mechanisms.

Condition

IP Behavior

Reporting Mechanism Recovering Mechanism

Source Core

Burst gap error

The source detects the burst gap between two consecutive bursts does not match Required idle cycles between bursts parameter setting.

The source core asserts the error flag for one clock cycle.

  • tx_burst_gap_err of TX Error Status register set to 1 (only for Stratix® 10 devices).
  • error/error_tx[3] signal asserted.
  • err_interrupt/err_interrupt_tx signal asserted (only available when tx_burst_gap_err_en of TX Error Interrupt Enable register is set to 1 (only for Stratix® 10 devices).
Make sure the burst gap of the incoming packet is matching the Required idle cycles between burstsparameter.

Rate adaptation FIFO buffer overflow in source interface.

There is an overflow on the rate adaptation FIFO buffer in the source interface. The core behavior depends on the operation mode:

  • Continuous mode—error is flagged once an overflow is detected.
  • Burst mode—error is flagged only when an overflow occurs during burst data transfer across the user interface.

The source core asserts the error flag when the FIFO is in overflow condition.

  • adapt_fifo_overflow of TX Error Status register set to 1 (only for Stratix® 10 devices).
  • error/error_tx[0] signal asserted.
  • err_interrupt/err_interrupt_tx signal asserted (only available when adapt_fifo_overflow_en of TX Error Interrupt Enable register is set to 1 (only for Stratix® 10 devices).
  • Assert phy_mgmt_clk_reset to reset the IP.
  • Send empty cycle to prevent FIFO overflow.

ECC fatal error.

The source core asserts the error flag for one clock cycle when a double bit error is detected.

  • ecc_err_fatal of TX Error Status register set to 1 (only for Stratix® 10 devices).
  • error/error_tx[2] signal asserted.
  • err_interrupt/err_interrupt_tx signal asserted (only available when ecc_err_fatal_en of TX Error Interrupt Enable register is set to 1 (only for Stratix® 10 devices).
Assert phy_mgmt_clk_reset signal to reset the IP.

ECC corrected error.

The source core asserts the error flag for one clock cycle when a single bit error is detected and corrected.

  • ecc_err_corrected of TX Error Status register set to 1 (only for Stratix® 10 devices).
  • error/error_tx[1] signal asserted.
  • err_interrupt/err_interrupt_tx signal asserted (only available when ecc_err_corrected_en of TX Error Interrupt Enable register is set to 1 (only for Stratix® 10 devices).
—
Source lost of lane alignment error

The source core detects a loss of lane alignment during normal operation.

  • tx_sync_done_lost of TX Error Status register set to 1 (only for Stratix® 10 devices).
  • err_interrupt/err_interrupt_tx signal asserted (only available when tx_sync_donelost_en of TX Error Interrupt Enable register is set to 1 (only for Stratix® 10 devices).

The source core automatically re-initialize the link when this error occurs.

Optionally, you can assert phy_mgmt_clk_reset to reset the IP.

Sink Core

RX data error

When the sink interface receives data but ready_rx signal is de-asserted.

  • rx_data_err of RX Error Status register set to 1 (only for Stratix® 10 devices).
  • err_interrupt/err_interrupt_rx signal asserted (only available when rx_data_err_int_en of RX Error Interrupt Enable register is set to 1 (only for Stratix® 10 devices).
—
Lane deskew fatal error

The sink core detects an error when the lane skews across all lanes exceeded the hardware de-skew capability.

  • rx_deskew_fatal of RX Error Status register set to 1 (only for Stratix® 10 devices).
  • err_interrupt/err_interrupt_rx signal asserted (only available when rx_deskew_fatal_int_en of RX Error Interrupt Enable register is set to 1 (only for Stratix® 10 devices).

Assert phy_mgmt_clk_reset to reset the IP. Ensure the board routing does not exceed 107 UI.

ECC fatal error.

The sink core asserts the error flag for one clock cycle when a double bit error is detected.

  • ecc_err_fatal of RX Error Status register set to 1 (only for Stratix® 10 devices).
  • error/error_rx[N+4] signal asserted.
  • err_interrupt/err_interrupt_rx signal asserted (only available when ecc_err_fatal_int_en of RX Error Interrupt Enable register is set to 1 (only for Stratix® 10 devices).
Assert phy_mgmt_clk_reset signal to reset the IP.

ECC corrected error.

The sink core asserts the error flag for one clock cycle when a single bit error is detected and corrected.

  • ecc_err_corrected of RX Error Status register set to 1 (only for Stratix® 10 devices).
  • error/error_rx[N+3] signal asserted.
  • err_interrupt/err_interrupt_rx signal asserted (only available when ecc_err_corrected_int_en of RX Error Interrupt Enable register is set to 1 (only for Stratix® 10 devices).
—

Rate adaptation FIFO buffer overflow

There is an overflow on the rate adaptation FIFO buffer in the sink interface. The core behavior depends on the operation mode:

  • Continuous mode—error is flagged once an overflow is detected.
  • Burst mode—error is flagged only when an overflow occurs during burst data transfer across the user interface.

The sink core asserts the error flag when the FIFO is in overflow condition.

  • adapt_fifo_overflow of RX Error Status register set to 1 (only for Stratix® 10 devices).
  • error/error_rx[N+2] signal asserted.
  • err_interrupt/err_interrupt_rx signal asserted (only available when adapt_fifo_over_flow_int_en of RX Error Interrupt Enable register is set to 1 (only for Stratix® 10 devices).
—

Lane alignment failure during normal operation

The sink core detects a loss of lane alignment during normal operation.

The sink core asserts error[N]5 flag for one clock cycle.

  • rx_alignment_lostlock of RX Error Status register set to 1 (only for Stratix® 10 devices).
  • error/error_rx[N] signal asserted.
  • err_interrupt/err_interrupt_rx signal asserted (only available when rx_alignment_lostlock_int_en of RX Error Interrupt Enable register is set to 1 (only for Stratix® 10 devices).

The sink core automatically re-initialize and re-align the link.

Optionally, you can assert phy_mgmt_clk_reset to reset the IP.

RX PCS Error

One or more errors have occurred in a given meta-frame, as determined by Native PHY PCS logic (in Interlaken mode).

These errors could be triggered much later (with respect to the user packets received earlier) at the receiving link.

Note: If data integrity is critical, additional error checksum may be included in the user logic as part of data payload so that the downstream user logic can determine the data integrity at packet level.
  • rx_pcs_err of RX Error Status register set to 1 (only for Stratix® 10 devices).
  • error/error_rx[N-1:0] signal asserted.
  • err_interrupt/err_interrupt_rx signal asserted (only available when rx_pcs_err_int_en of RX Error Interrupt Enable register is set to 1 (only for Stratix® 10 devices).
—

Diagnostic code word CRC-32 error

The sink core detects a metaframe CRC-32 error on one of the lanes. These errors are reported on a per-lane basis for diagnostic purposes.

The sink core asserts error[N-1:0]5 flag for one clock cycle.

  • rx_crc32err of RX Error Status register set to 1 (only for Stratix® 10 devices).
  • error/error_rx[N-1:0] signal asserted.
  • err_interrupt/err_interrupt_rx signal asserted (only available when rx_crc32err_int_en of RX Error Interrupt Enable register is set to 1 (only for Stratix® 10 devices).
—
5 N is the number of lanes.
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