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1.1. Directory Structure
1.2. Generating the Design
1.3. Simulating the H-Tile Hard IP for Ethernet Intel FPGA Design Example Testbench
1.4. Compiling the Compilation-Only Project
1.5. Compiling and Configuring the Design Example in Hardware
1.6. Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
2.1. H-Tile Hard IP for Ethernet Intel FPGA MAC + PCS Simulation Design Example
2.2. H-Tile Hard IP for Ethernet Intel FPGA PCS Only Simulation Design Example
2.3. H-Tile Hard IP for Ethernet Intel FPGA OTN Simulation Design Example
2.4. H-Tile Hard IP for Ethernet Intel FPGA FlexE Simulation Design Example
2.5. Hardware Design Example Components
2.6. Design Example Interface Signals
2.7. H-Tile Hard IP for Ethernet Intel FPGA Design Example Registers
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1.4. Compiling the Compilation-Only Project
To compile the compilation-only example project, follow these steps:
- Ensure compilation design example generation is complete.
- In the Intel® Quartus® Prime Pro Edition software, open the Intel® Quartus® Prime Pro Edition project <design_example_dir>/compilation_test_design/alt_ehipc2.qpf.
- On the Processing menu, click Start Compilation.
After successful compilation, reports for timing and for resource utilization are available in your Intel® Quartus® Prime Pro Edition session.
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