H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683314
Date 1/27/2021
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Document Archives 5. Document Revision History for the H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the H-Tile Hard IP for Ethernet Intel FPGA Design Example Testbench 1.4. Compiling the Compilation-Only Project 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
1.6. Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example x
1.6.1. Testing the Hardware Design Example using Ethernet Link Inspector
2. Design Example Description x
2.1. H-Tile Hard IP for Ethernet Intel FPGA MAC + PCS Simulation Design Example 2.2. H-Tile Hard IP for Ethernet Intel FPGA PCS Only Simulation Design Example 2.3. H-Tile Hard IP for Ethernet Intel FPGA OTN Simulation Design Example 2.4. H-Tile Hard IP for Ethernet Intel FPGA FlexE Simulation Design Example 2.5. Hardware Design Example Components 2.6. Design Example Interface Signals 2.7. H-Tile Hard IP for Ethernet Intel FPGA Design Example Registers
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Document Archives
5. Document Revision History for the H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

2.4. H-Tile Hard IP for Ethernet Intel FPGA FlexE Simulation Design Example

Figure 9.  H-Tile Hard IP for Ethernet Intel FPGA 100 Gbps FlexE Simulation Design Example Block Diagram

The testbench sends traffic through the IP core with FlexE mode, exercising the transmit and receive PCS66 interfaces using a separate H-Tile Hard IP for Ethernet Intel FPGA MAC as a stimulus generator. The PCS66 interface of the FlexE core is connected to a synchronous FIFO that receives PCS66 data and alignment marker valid signals. The FIFO then writes back to the PCS66 transmit interface,

The simulation design example instantiates a main ATX PLL for transceiver channel 0 and 1, and a clock buffer for channel 2 and 3.

The testbench in this design example performs the following:

  1. The client logic resets both the IP cores.
  2. The stimulus client logic waits for the stimulus RX datapath and FlexE RX datapath to align.
  3. Once alignment is complete, the stimulus client logic transmits a series of packets to the FlexE IP core.
  4. The FlexE IP core receives the series of packets and transmits back to the stimulus MAC IP core.
  5. The stimulus client logic then checks the number of packets received and verifies that the packets have no errors.
The following sample output illustrates a successful simulation test run for a 100 Gbps FlexE IP core variation. Times are in picoseconds. 
# Ref clock is 644.53125 MHz
# Ref clock is 644.53125 MHz
# iatpg_pipeline_global_en is set
.
.
.
# iatpg_pipeline_global_en is set
# test_dut:waiting for o_tx_lanes_stable...
# dut:waiting for o_tx_lanes_stable...
# test_dut:o_tx_lanes_stable is 1 at time                525000
# test_dut:waiting for tx_dll_lock....
# dut:o_tx_lanes_stable is 1 at time                525000
# dut:waiting for tx_dll_lock....
# dut:TX DLL LOCK is 1 at time              47806703
# dut:waiting for tx_transfer_ready....
# dut:TX transfer ready is 1 at time              48126575
# dut:waiting for rx_transfer_ready....
# dut:RX transfer ready is 1 at time              59518683
# dut:EHIP PLD Ready out is 1 at time              59576000
# dut:EHIP reset out is 0 at time              59840000
# dut:EHIP reset ack is 0 at time              60151763
# dut:EHIP TX reset out is 0 at time              60488000
# dut:EHIP TX reset ack is 0 at time             110085115
# dut:waiting for EHIP Ready....
# dut:EHIP READY is 1 at time             110178411
# dut:EHIP RX reset out is 0 at time             110520000
# dut:waiting for rx reset ack....
# dut:EHIP RX reset ack is 0 at time             110578251
# dut:Waiting for RX Block Lock
# test_dut:TX DLL LOCK is 1 at time             124725923
# test_dut:waiting for tx_transfer_ready....
# test_dut:TX transfer ready is 1 at time             125045795
# test_dut:waiting for rx_transfer_ready....
# test_dut:RX transfer ready is 1 at time             136437903
# test_dut:EHIP PLD Ready out is 1 at time             136496000
# test_dut:EHIP reset out is 0 at time             136760000
# test_dut:EHIP reset ack is 0 at time             137070983
# test_dut:EHIP TX reset out is 0 at time             137408000
# test_dut:EHIP TX reset ack is 0 at time             187001003
# test_dut:waiting for EHIP Ready....
# test_dut:EHIP READY is 1 at time             187107627
# test_dut:EHIP RX reset out is 0 at time             187448000
# test_dut:waiting for rx reset ack....
# test_dut:EHIP RX reset ack is 0 at time             187507467
# test_dut:Waiting for RX Block Lock
# dut:EHIP RX Block Lock  is high at time             189300083
# dut:Waiting for AM lock
# dut:EHIP RX AM Lock  is high at time             190566243
# dut:Waiting for RX alignment
# dut:RX deskew locked
# dut:RX lane aligmnent locked
# dut:**
# dut:** Testbench complete.
# dut:**
# dut:*****************************************
# test_dut:EHIP RX Block Lock  is high at time             195472613
# test_dut:Waiting for AM lock
# test_dut:EHIP RX AM Lock  is high at time             196580503
# test_dut:Waiting for RX alignment
# test_dut:RX deskew locked
# test_dut:RX lane aligmnent locked
# dut:RX deskew locked
# dut:RX lane aligmnent locked
# test_dut:TX enabled
# test_dut: ** Sending Packet           1...
# test_dut: ** Sending Packet           2...
# test_dut: ** Sending Packet           3...
# test_dut: ** Sending Packet           4...
# test_dut: ** Sending Packet           5...
# test_dut: ** Sending Packet           6...
# test_dut: ** Sending Packet           7...
# test_dut: ** Sending Packet           8...
# test_dut: ** Sending Packet           9...
# test_dut: ** Sending Packet          10...
# test_dut: ** Received Packet          1...
# test_dut: ** Received Packet          2...
# test_dut: ** Received Packet          3...
# test_dut: ** Received Packet          4...
# test_dut: ** Received Packet          5...
# test_dut: ** Received Packet          6...
# test_dut: ** Received Packet          7...
# test_dut: ** Received Packet          8...
# test_dut: ** Received Packet          9...
# test_dut: ** Received Packet         10...
# test_dut:**
# test_dut:** Testbench complete.
# test_dut:**
# test_dut:*****************************************
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