H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683314
Date 1/27/2021
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Document Archives 5. Document Revision History for the H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the H-Tile Hard IP for Ethernet Intel FPGA Design Example Testbench 1.4. Compiling the Compilation-Only Project 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
1.6. Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example x
1.6.1. Testing the Hardware Design Example using Ethernet Link Inspector
2. Design Example Description x
2.1. H-Tile Hard IP for Ethernet Intel FPGA MAC + PCS Simulation Design Example 2.2. H-Tile Hard IP for Ethernet Intel FPGA PCS Only Simulation Design Example 2.3. H-Tile Hard IP for Ethernet Intel FPGA OTN Simulation Design Example 2.4. H-Tile Hard IP for Ethernet Intel FPGA FlexE Simulation Design Example 2.5. Hardware Design Example Components 2.6. Design Example Interface Signals 2.7. H-Tile Hard IP for Ethernet Intel FPGA Design Example Registers
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Document Archives
5. Document Revision History for the H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

5. Document Revision History for the H-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.01.27 20.3 19.3.0 Added new topic: Ethernet Toolkit
2020.06.22 20.2 19.3.0
  • Updated the Quick Start Guide section:
    • Added User Guide link
    • Added Release Notes link
  • Removed 50-Gbps Ethernet variant support.
2019.10.31 19.3 19.2.0
  • Changed 0x104 register's name from Source address lower 16 bits to Source address upper 16 bits in the Packet Client Registers table.
  • Added Xcelium* and Synopsys VCS* MX simulators support.
  • Updated Generating the Design section:
    • Updated the Example Design Tab in the H-tile Hard IP for Ethernet Intel FPGA Parameter Editor figure
    • Added parameter: PHY Reference Frequency
    • Replaced Enable Altera Debug Master endpoint parameter with Enable Altera Debug Master endpoint
    • Added parameter: Enable JTAG to Avalon Master Bridge
    • Updated target development kit to Stratix 10 MX FPGA Development Kit
    • Added step to select the Target Device
  • Updated the Steps to Simulate the Testbench table:
    • Added instruction for Xcelium* and Synopsys VCS* MX simulator
    • Added note to clarify run_vcs.sh and run_vcsmx.sh usage
  • Updated the Intel Stratix 10 MX FPGA Development Kit Hardware Design Example High Level Block Diagram figure in the Hardware Design Example Components.
  • Updated target development kit to Stratix 10 MX FPGA Development Kit in the Hardware Design Example Components section.
  • Added the Testing the Hardware Design Example using Ethernet Link Inspector.
2019.04.01 19.1 19.1 Removed information about Intel Stratix 10 GXT Transceiver SoC development kit in the Generating the Design and Hardware Design Example Components sections. The H-tile Hard IP for Ethernet Intel FPGA IP version 19.1 does not support Intel Stratix 10 GXT Transceiver SoC development kit.
2019.01.21 18.1 18.1
  • Changed the image of the H-tile Hard IP for Ethernet FPGA IP design example parameter editor to reflect the latest version.
  • Updated the Compiling and Configuring the Design Example in Hardware, Design Example Description, and Hardware Design Example Components sections to include that the hardware design example now supports PCS Only variants.
  • Edited the successful test behavior description for PCS Only variant in the Simulating the H-tile Hard IP for Ethernet Intel FPGA Design Example Testbench section. A successful test run sends hundred packets for PCS Only variants.
  • Added the Testing the Hardware Design Example in PCS Only Mode section.
  • Edited the Intel Stratix 10 GXT Transceiver Signal Integrity and Intel Stratix 10 GXT Transceiver SoC development kit hardware design example diagrams to add PCS Only variant and remove RS-FEC. The current version does not support the Reed Solomon Forward Error Correction (RS-FEC) feature.
2018.08.10 18.0 18.0
  • Added design example testbench components and test behavior for OTN and FlexE variations.
  • Added hardware design example components and test behavior.
  • Added hardware design example register description.
  • Rebranded the IP core name from Intel® Stratix® 10 H-Tile Hard IP for Ethernet IP core to H-Tile Hard IP for Ethernet Intel FPGA per Intel rebranding.
2017.11.29 17.1 17.1 Initial release.
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