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1.1. Directory Structure
1.2. Generating the Design
1.3. Simulating the H-Tile Hard IP for Ethernet Intel FPGA Design Example Testbench
1.4. Compiling the Compilation-Only Project
1.5. Compiling and Configuring the Design Example in Hardware
1.6. Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
2.1. H-Tile Hard IP for Ethernet Intel FPGA MAC + PCS Simulation Design Example
2.2. H-Tile Hard IP for Ethernet Intel FPGA PCS Only Simulation Design Example
2.3. H-Tile Hard IP for Ethernet Intel FPGA OTN Simulation Design Example
2.4. H-Tile Hard IP for Ethernet Intel FPGA FlexE Simulation Design Example
2.5. Hardware Design Example Components
2.6. Design Example Interface Signals
2.7. H-Tile Hard IP for Ethernet Intel FPGA Design Example Registers
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1.6.1. Testing the Hardware Design Example using Ethernet Link Inspector
You can also test your design using the Ethernet Link Inspector (ELI) tool available in System console.
Design examples have built-in JTAG to AVMM bridge allowing you to use the Ethernet Link Inspector. Refer to the user guide on how to use the ELI to test your design.
The ELI tool is accessible via System Console in the Tools > Legacy Toolkits in the Intel® Quartus® Prime Pro Edition software.
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