2.3. H-Tile Hard IP for Ethernet Intel FPGA OTN Simulation Design Example
Figure 8. H-Tile Hard IP for Ethernet Intel FPGA OTN Simulation Design Example Block Diagram
Note: The H-Tile Hard IP for Ethernet Intel FPGA IP provides preliminary support for the OTN feature. For further inquiries, contact your nearest Intel sales representative or file an Intel Premier Support (IPS) case on https://www.intel.com/content/www/us/en/programmable/my-intel/mal-home.html.
The testbench sends traffic through the IP core with OTN mode, exercising the transmit and receive PCS66 interfaces using a separate H-Tile Hard IP for Ethernet Intel FPGA MAC as a stimulus generator.
The simulation design example instantiates a main ATX PLL for transceiver channel 0 and 1, and a clock buffer for channel 2 and 3.
The testbench in this design example performs the following:
- The client logic resets both the IP cores.
- The stimulus client logic waits for the stimulus RX datapath and OTN RX datapath to align.
- Once alignment is complete, the stimulus client logic transmits a series of packets to the OTN IP core.
- The OTN IP core receives the series of packets and transmits back to the stimulus MAC IP core.
- The stimulus client logic then checks the number of packets received and verifies that the packets have no errors.
The following sample output illustrates a successful simulation test run for a 100 Gbps OTN IP core variation. Times are in picoseconds.
# Ref clock is 644.53125 MHz
# Ref clock is 644.53125 MHz
# iatpg_pipeline_global_en is set
.
.
.
# iatpg_pipeline_global_en is set
# test_dut:waiting for o_tx_lanes_stable...
# dut:waiting for o_tx_lanes_stable...
# test_dut:o_tx_lanes_stable is 1 at time 525000
# test_dut:waiting for tx_dll_lock....
# dut:o_tx_lanes_stable is 1 at time 525000
# dut:waiting for tx_dll_lock....
# dut:TX DLL LOCK is 1 at time 47806703
# dut:waiting for tx_transfer_ready....
# dut:TX transfer ready is 1 at time 48126575
# dut:waiting for rx_transfer_ready....
# dut:RX transfer ready is 1 at time 59518683
# dut:EHIP PLD Ready out is 1 at time 59576000
# dut:EHIP reset out is 0 at time 59840000
# dut:EHIP reset ack is 0 at time 60151763
# dut:EHIP TX reset out is 0 at time 60488000
# dut:EHIP TX reset ack is 0 at time 110085115
# dut:waiting for EHIP Ready....
# dut:EHIP READY is 1 at time 110178411
# dut:EHIP RX reset out is 0 at time 110520000
# dut:waiting for rx reset ack....
# dut:EHIP RX reset ack is 0 at time 110578251
# dut:Waiting for RX Block Lock
# test_dut:TX DLL LOCK is 1 at time 124725923
# test_dut:waiting for tx_transfer_ready....
# test_dut:TX transfer ready is 1 at time 125045795
# test_dut:waiting for rx_transfer_ready....
# test_dut:RX transfer ready is 1 at time 136437903
# test_dut:EHIP PLD Ready out is 1 at time 136496000
# test_dut:EHIP reset out is 0 at time 136760000
# test_dut:EHIP reset ack is 0 at time 137070983
# test_dut:EHIP TX reset out is 0 at time 137408000
# test_dut:EHIP TX reset ack is 0 at time 187001003
# test_dut:waiting for EHIP Ready....
# test_dut:EHIP READY is 1 at time 187107627
# test_dut:EHIP RX reset out is 0 at time 187448000
# test_dut:waiting for rx reset ack....
# test_dut:EHIP RX reset ack is 0 at time 187507467
# test_dut:Waiting for RX Block Lock
# dut:EHIP RX Block Lock is high at time 189300083
# dut:Waiting for AM lock
# dut:EHIP RX AM Lock is high at time 190566243
# dut:Waiting for RX alignment
# dut:RX deskew locked
# dut:RX lane aligmnent locked
# dut:**
# dut:** Testbench complete.
# dut:**
# dut:*****************************************
# test_dut:EHIP RX Block Lock is high at time 194839533
# test_dut:Waiting for AM lock
# test_dut:EHIP RX AM Lock is high at time 196580503
# test_dut:Waiting for RX alignment
# test_dut:RX deskew locked
# test_dut:RX lane aligmnent locked
# dut:RX deskew locked
# dut:RX lane aligmnent locked
# test_dut:TX enabled
# test_dut: ** Sending Packet 1...
# test_dut: ** Sending Packet 2...
# test_dut: ** Sending Packet 3...
# test_dut: ** Sending Packet 4...
# test_dut: ** Sending Packet 5...
# test_dut: ** Sending Packet 6...
# test_dut: ** Sending Packet 7...
# test_dut: ** Sending Packet 8...
# test_dut: ** Sending Packet 9...
# test_dut: ** Received Packet 1...
# test_dut: ** Sending Packet 10...
# test_dut: ** Received Packet 2...
# test_dut: ** Received Packet 3...
# test_dut: ** Received Packet 4...
# test_dut: ** Received Packet 5...
# test_dut: ** Received Packet 6...
# test_dut: ** Received Packet 7...
# test_dut: ** Received Packet 8...
# test_dut: ** Received Packet 9...
# test_dut: ** Received Packet 10...
# test_dut:**
# test_dut:** Testbench complete.
# test_dut:**
# test_dut:*****************************************