1.6. Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
After you compile the H-Tile Hard IP for Ethernet Intel FPGA IP core design example and configure it on your Intel® Stratix® 10 device, you can use the System Console to program the IP core and its embedded Native PHY IP core registers.
You can test the H-Tile Hard IP for Ethernet Intel FPGA IP hardware design example in either MAC + PCS mode or PCS Only mode.
Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example in MAC + PCS Mode
To turn on the System Console and test the hardware design example, follow these steps:
- After the hardware design example is configured on the Intel® Stratix® 10 device, in the Intel® Quartus® Prime Pro Edition software, click .
- In the Tcl Console pane, type cd hwtest to change directory to <design_example_dir>/hardware_test_design/hwtest.
- Type source main.tcl to open a connection to the JTAG master.
You can program the IP core with the following design example commands:
- chkphy_status: Displays the clock frequencies and PHY lock status.
- chkmac_stats: Displays the values in the MAC statistics counters.
- clear_all_stats: Clears the IP core statistics counters.
- start_pkt_gen: Starts the packet generator.
- stop_pkt_gen: Stops the packet generator.
- loop_on: Turns on internal serial loopback
- loop_off: Turns off internal serial loopback.
- reg_read <addr>: Returns the IP core register value at <addr>.
- reg_write <addr> <data>: Writes <data> to the IP core register at address <addr>.
Testing the H-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example in PCS Only Mode
The PCS Only design has its own MII packet generator, which is different from the MAC+PCS design packet generator.
You can run this packet generator in three modes:
- incremental mode
- constant mode (value configurable via the top level)
- random packet content mode
After you compile the PCS Only design example and configure it on your Intel® Stratix® 10 device, you can use the System Console to program the IP core and its embedded Native PHY IP registers.
- After the hardware design example is configured on the Intel® Stratix® 10 device, in the Intel® Quartus® Prime Pro Edition software, click .
- In the Tcl Console pane, type cd hwtest to change directory to <design_example_dir>/hardware_test_design/hwtest.
- Type source main.tcl to open a connection to the JTAG master.
- Copy the Example Script below to the hwtest directory and save as pcs_only_traffic_test.tcl.
- Type source pcs_only_traffic_test.tcl.
- Check the traffic by sending and receiving packets by the running the command below:
pcs_only_traffic_test 10 (this command should transmit and receive 10 packets).
Functions | Bits | Description |
---|---|---|
Base register | 0xf000 | The base register for the PCS packet generator command. |
proc start_pcs_pkt_gen | 0x0 0x01 |
Starting the packet generator. |
proc read_pcs_pkt_gen | 0x2 | Reading the results. |
proc pcs_gen_num_frames | 0x6 num_frames | Setting the number of frames to send |
proc get_pcs_gen_num_frames | 0x6 | Getting the number of frames |
proc pcs_gen_frame_size | 0x7 frame_size | Setting the size of frames to send |
proc get_pcs_gen_frame_size | 0x7 | Getting the size of frames |
proc get_pcs_gen_match_count | 0x8 | Getting the number of matched frames |
proc get_pcs_gen_mismatch_count | 0x9 | Getting the number of mismatched frames |
proc pcs_gen_set_frame_type | Frame type = Incr; 0xa 0x1 Frame type = constant; 0xa 0x3 Frame type = random; 0xa 0x4 |
Changing the type of frame
|
To access the registers, use reg_read or reg_write. For example:
To start the generator: reg_write 0xf000 0x0 0x01
To write to the number of frames register: reg_write 0xf000 0x6 $num_frames
Example Script
This example script includes the functions listed in the Table 4 table and a traffic test that runs in loopback mode and randomly picks a number (30 – 16,384) of frames to send, size of frames, and type of frame to send.
set log_file_handle [open loopback_test_results.log w]
source main.tcl
set PCS_pkt_client_base 0xf000
set frame_type_list { "incr" "constant" "random"}
proc hard_reset { }
{
open_issp *
sp_assert_reset
sp_deassert_reset
close_issp
}
proc random_element { list } {
lindex $list [expr {int (rand()* [llength $list])}]
}
proc random { {min 30 } { max 100 } } \
{
return [expr {int($min + rand() * $max)}]
}
proc start_pcs_pkt_gen { } \
{
variable PCS_pkt_client_base
reg_write $PCS_pkt_client_base 0x0 0x01
}
proc read_pcs_pkt_gen { } \
{
variable PCS_pkt_client_base
set res [reg_read $PCS_pkt_client_base 0x2]
return $res
}
proc pcs_gen_num_frames { { num_frames 200} } \
{
variable PCS_pkt_client_base
reg_write $PCS_pkt_client_base 0x6 $num_frames
}
proc get_pcs_gen_num_frames { } \
{
variable PCS_pkt_client_base
reg_read $PCS_pkt_client_base 0x6
}
proc pcs_gen_frame_size { { frame_size 200} } \
{
variable PCS_pkt_client_base
reg_write $PCS_pkt_client_base 0x7 $frame_size
}
proc get_pcs_gen_frame_size { } \
{
variable PCS_pkt_client_base
reg_read $PCS_pkt_client_base 0x7
}
proc get_pcs_gen_match_count { } \
{
variable PCS_pkt_client_base
reg_write $PCS_pkt_client_base 0x8
}
proc get_pcs_gen_mismatch_count { } \
{
variable PCS_pkt_client_base
reg_read $PCS_pkt_client_base 0x9
}
proc pcs_gen_set_frame_type { {frame_type "incr"} } \
{
variable PCS_pkt_client_base
if {$frame_type == "incr"} {
reg_write $PCS_pkt_client_base 0xa 0x1
} elseif { $frame_type == "constant" } {
reg_write $PCS_pkt_client_base 0xa 0x3
} elseif { $frame_type == "random" } {
reg_write $PCS_pkt_client_base 0xa 0x4
} else {
puts "ERROR"
return -1
}
return 0
}
proc pcs_only_traffic_test { iterations } {
variable log_file_handle
variable frame_type_list
set test_name [lindex [info level [info level]] 0]
puts "Running ${test_name} test"
after 100
#hard_reset
chkphy_status
set phy_locked [phy_locked]
puts "Phy locked status is $phy_locked "
# global $CLIENT_BASE
set PCS_pkt_client_base 0xf000
for {set i 0} {$i < $iterations} {incr i} {
#randomize some stuff. Like number and size of Frames
set res [random 30 16384]
puts "Setting Number of frames to $res\n"
pcs_gen_num_frames $res
set res [random 30 16384]
puts "Setting Size of frames to $res\n"
pcs_gen_frame_size $res
set res [random_element $frame_type_list]
puts "Setting Type of frames to $res\n"
pcs_gen_set_frame_type $res
puts "PCS TRAFFIC = ${i}"
start_pcs_pkt_gen
after 1000
set res [read_pcs_pkt_gen]
if { $res == 0x53} {
puts "${test_name}:pass"
} else {
puts "${test_name}:fail, Got $res instead of 0x53"
puts $log_file_handle "${test_name}:fail, Got $res instead of 0x53"
return -1
}
}
puts $log_file_handle "${test_name}:pass"
return 0
}
proc pcs_gen_result { } \
{
variable PCS_pkt_client_base
set pass [read_pcs_pkt_gen]
set max_frames [reg_read $PCS_pkt_client_base 0x6]
set frame_size [reg_read $PCS_pkt_client_base 0x7]
set match_count [reg_read $PCS_pkt_client_base 0x8]
set mismatch_count [reg_read $PCS_pkt_client_base 0x9]
set frame_type [reg_read $PCS_pkt_client_base 0xa]
if { $pass == 0x53} {
puts "Last test passed!\n"
} else {
puts "Last test failed, Got $pass instead of 0x53"
}
puts "Num of frames = $max_frames"
puts "Frame size = $frame_size"
puts "Match count = $match_count"
puts "Mismatch count = $mismatch_count"
if {$frame_type == 0x1} {
puts "Frame Type = incr"
} elseif { $frame_type == 0x9 } {
puts "Frame type = constant_crc"
} elseif { $frame_type == 0x3 } {
puts "Frame type = constant"
} elseif { $frame_type == 0x4 } {
puts "Frame type = random"
}
}