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Ixiasoft
1.1. Block-Based Design Terminology
This document refers to the following terms to explain block-based design methods:
Term | Description |
---|---|
Black Box File | RTL source file that contains only port and module or entity definitions, without any logic. Include parameters or generics passed to the module or entity to ensure that the configuration matches the implementation in the Consumer project. |
Block |
Logic that comprises a hierarchical design instance, typically represented by a Verilog module or VHDL entity. You designate a design block as a design partition to preserve, empty, or export the block. |
Consumer | A Consumer can reuse a design partition that a Developer exports as a Partition Database File (.qdb) from another project. |
Core Partition | A design partition that contains only FPGA resources for the implementation of core logic, such as LUTs, registers, M20K memory blocks, and DSPs. A core partition cannot include periphery resources. |
Design Partition |
A logical, named, hierarchical boundary assignment that you can apply to a design instance. Creating a partition creates a logical boundary and prevents logic optimization and merging with parent or child partitions. Design partitions facilitate incremental block-based compilation and design block reuse by logically separating instances. |
Developer | A Developer creates and exports a design partition as a .qdb for use in a Consumer project. |
Fast Preserve | The Fast Preserve Compiler option simplifies the logic of a preserved partition to only interface logic during compilation, thereby reducing the compilation time for the partition. |
Floorplanning |
Planning the physical layout of FPGA device resources. The manual process of assigning the logical design hierarchy and periphery to physical regions in the device and I/O. |
Logic Lock Region Constraints |
Constrains the placement and routing of logic to a specific region in the target device. Specify the region origin, height, width, and any of the following options:
|
Preservation |
The Compiler can preserve a snapshot of compilation results, for each partition, at specific stages of compilation. You can preserve design blocks after synthesis or after the final stage of the Fitter. |
Project |
The Intel® Quartus® Prime software organizes the source files, settings, and constraints within a project of one or more revisions. The Intel® Quartus® Prime Project File (.qpf) stores the project name and references each project revision that you create. |
Root Partition |
The Intel® Quartus® Prime software automatically creates a top-level "root_partition" with a hierarchy path of |for each project revision. The root partition includes all device periphery resources (such as I/O, HSSIO, memory interfaces, and PCIe*) and associated core resources. You can export and reuse periphery resources by exporting the root partition and reserving a region for subsequent development (the reserved core) by a Consumer. |
Snapshot |
A snapshot is a view of the design after a compilation stage. The Intel® Quartus® Prime Compiler generates a snapshot of the compilation database after each compilation stage. You can preserve or export a specific snapshot for incremental block-based compilation, design block reuse, and team based designs. |