Low Latency Ethernet 10G MAC Intel® FPGA IP Release Notes

ID 683308
Date 10/07/2024
Public
Document Table of Contents

Low Latency Ethernet 10G MAC Intel® FPGA IP (intel_eth_em10g32) v3.0.0

Table 1.  v3.0.0 2024.10.07
Quartus® Prime Version Description Impact
24.3
  • Added the following design example for Agilex™ 5 devices;
    • 1G ethernet design example with IEEE 1588v2 feature
    • 2.5G ethernet design example with IEEE 1588v2 feature
    • 10G ethernet design example
  • Added hardware support for the following design example:
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Design Example
  • Added support for Riviera-PRO* simulator for the following design example:
    • 10M/100M/1G ethernet design example
    • 1G ethernet design example with IEEE 1588v2 feature
    • 2.5G ethernet design example
    • 2.5G ethernet design example with IEEE 1588v2 feature
    • 10G ethernet design example
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) ethernet design example
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) ethernet design example with IEEE 1588 design example
  • Support for Agilex™ 5 D-Series FPGAs and SoCs is no longer restricted.