FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

Download PDF
ID 683292
Date 8/18/2021
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. FIM and AFU Parameter Data 3. FPGA Interface Manager (FIM) Resource Utilization 4. Document Revision History for FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA
2. FIM and AFU Parameter Data x
2.1. Memory Interface 2.2. Core Cache Interface (CCI-P) Interface 2.3. Clocks 2.4. Reset 2.5. Networking Interface
2.1. Memory Interface x
2.1.1. SDRAM Signals
2.5. Networking Interface x
2.5.1. Clock Signals 2.5.2. Data Interface and Signals 2.5.3. Control and Status Signals
1. Overview
2. FIM and AFU Parameter Data
3. FPGA Interface Manager (FIM) Resource Utilization
4. Document Revision History for FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

2.1.1. SDRAM Signals

This table defines the interface for each of the two DDR4 memories from the viewpoint of the AFU.
Table 2.  SDRAM Interface
Signal Name Direction (AFU viewpoint) Width Description
clk input 1 Provides synchronization for internal logic.
waitrequest input 1 Asserts when the EMIF controller is unable to respond to a read or write request.
readdata input 512 Read data signal from the DDR4 to the AFU.
readdatavalid input 1 Used for variable-latency, pipelined read transfers. When asserted, indicates that the readdata signal contains valid data.
burstcount output 7 Used to indicate the number of transfers in each burst.
writedata output 512 Write data signal to the external DDR4.
address output 27 By default, the interconnect translates the byte address into a word address in the slave’s address space. From the perspective of the slave, each slave access is for a word of data.
write output 1 Asserted to indicate a write transfer.
read output 1 Asserted to indicate a read transfer.
byteenable output 64 Enables one or more specific byte lanes during transfers on interfaces of width greater than 8 bits. Each bit in byteenable corresponds to a byte in writedata and readdata.
Level Two Title