FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683292
Date 8/18/2021
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. FIM and AFU Parameter Data 3. FPGA Interface Manager (FIM) Resource Utilization 4. Document Revision History for FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA
2. FIM and AFU Parameter Data x
2.1. Memory Interface 2.2. Core Cache Interface (CCI-P) Interface 2.3. Clocks 2.4. Reset 2.5. Networking Interface
2.1. Memory Interface x
2.1.1. SDRAM Signals
2.5. Networking Interface x
2.5.1. Clock Signals 2.5.2. Data Interface and Signals 2.5.3. Control and Status Signals
1. Overview
2. FIM and AFU Parameter Data
3. FPGA Interface Manager (FIM) Resource Utilization
4. Document Revision History for FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

2.3. Clocks

Table 4.  Clock Specifications
Parameter Value Notes
pClk 200 MHz

Primary interface clock. All CCI-P interface signals are synchronous to this clock.

pClkDiv2 100 MHz

Synchronous and in phase with pClk. 0.5x the pClk clock frequency.

pClkDiv4 50 MHz

Synchronous and in phase with pClk. 0.25x the pClk clock frequency.

uClk 312.5 MHz This clock can be adjusted by OPAE.
uClk/2 156.25 MHz This clock can be adjusted by OPAE.
uClk_usr Min 10 MHz Minimum user-defined clock. This clock is not synchronous with the pClk. You can adjust this clock using OPAE.
uClk_usr Default 312.5 MHz Default user-defined clock. This clock is not synchronous with the pClk. You can adjust this clock using OPAE.
uClk_usr Max 600 MHz Minimum user-defined clock. This clock is not synchronous with the pClk. You can adjust this clock using OPAE.
uClk_usrDiv2 Min 10 MHz

Minimum user defined clock that is synchronous with uClk_usr and 0.5x the frequency.

Note: You can use OPAE to set the frequency to a value that is not synchronous with the uClk_usr.
uClk_usrDiv2 Default 156.25 MHz

User defined clock that is synchronous with uClk_usr and 0.5x the frequency.

Note: You can use OPAE to set the frequency to a value that is not synchronous with the uClk_usr.
uClk_usrDiv2 Max 600 MHz

Maximum user defined clock that is synchronous with uClk_usr and 0.5x the frequency.

Note: You can use OPAE to set the frequency to a value that is not synchronous with the uClk_usr.
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