FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683292
Date 8/18/2021
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. FIM and AFU Parameter Data 3. FPGA Interface Manager (FIM) Resource Utilization 4. Document Revision History for FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA
2. FIM and AFU Parameter Data x
2.1. Memory Interface 2.2. Core Cache Interface (CCI-P) Interface 2.3. Clocks 2.4. Reset 2.5. Networking Interface
2.1. Memory Interface x
2.1.1. SDRAM Signals
2.5. Networking Interface x
2.5.1. Clock Signals 2.5.2. Data Interface and Signals 2.5.3. Control and Status Signals
1. Overview
2. FIM and AFU Parameter Data
3. FPGA Interface Manager (FIM) Resource Utilization
4. Document Revision History for FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

2.5.2. Data Interface and Signals

The HSSI unified data interface conforms to the Intel® Arria® 10 FPGA Transceiver Native PHY IP with enhanced PCS. It consists of generic parallel data and encoding control interfaces for transmit and receive that are mapped to specific signaling behavior based on the configured HSSI PHY mode. The unified data interface also includes flow control ports to manage passing data to and from the HSSI PHY.

The below table provides a cross reference from the hssi:raw_pr unified data interface signals to the Intel® Arria® 10 FPGA Transceiver Native PHY IP with enhanced PCS signal set. For detailed information on these signals, see the Intel Arria 10 Transceiver PHY User Guide as referenced in the below table.

Table 8.  Data Signals
Port Name Width Direction Clock Domain Native PHY IP Port Name
Transmit and Receive Data and Encoding Control Ports
a2f_tx_parallel_data (4*128) Input f2a_tx_clk tx_parallel_data
a2f_tx_control (4*18) Input f2a_tx_clk tx_control
f2a_rx_parallel_data (4*128) Output f2a_rx_clk_ln0 rx_parallel_data
f2a_rx_control (4*20) Output f2a_rx_clk_ln0 rx_control
Flow Control Ports
f2a_tx_enh_fifo_full 4 Output f2a_tx_clk tx_enh_fifo_full
f2a_tx_enh_fifo_pfull 4 Output f2a_tx_clk tx_enh_fifo_pfull
f2a_tx_enh_fifo_empty 4 Output f2a_tx_clk tx_enh_fifo_empty
f2a_tx_enh_fifo_pempty 4 Output f2a_tx_clk tx_enh_fifo_pempty
a2f_tx_enh_data_valid 4 Input f2a_tx_clk tx_enh_data_valid
f2a_rx_enh_fifo_full 4 Output f2a_rx_clk_ln0 rx_enh_fifo_full
f2a_rx_enh_fifo_pfull 4 Output f2a_rx_clk_ln0 rx_enh_fifo_pfull
f2a_rx_enh_fifo_empty 4 Output f2a_rx_clk_ln0 rx_enh_fifo_empty
f2a_rx_enh_fifo_pempty 4 Output f2a_rx_clk_ln0 rx_enh_fifo_pempty
f2a_rx_enh_data_valid 4 Output f2a_rx_clk_ln0 rx_enh_data_valid
a2f_rx_enh_fifo_rd_en 4 Input f2a_rx_clk_ln0 rx_enh_fifo_rd_en
f2a_rx_enh_fifo_pempty 4 Output f2a_rx_clk_ln0 rx_enh_fifo_pempty
f2a_rx_enh_data_valid 4 Output f2a_rx_clk_ln0 rx_enh_data_valid
a2f_rx_enh_fifo_rd_en 4 Input f2a_rx_clk_ln0 rx_enh_fifo_rd_en
Level Two Title