FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683292
Date 8/18/2021
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. FIM and AFU Parameter Data 3. FPGA Interface Manager (FIM) Resource Utilization 4. Document Revision History for FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA
2. FIM and AFU Parameter Data x
2.1. Memory Interface 2.2. Core Cache Interface (CCI-P) Interface 2.3. Clocks 2.4. Reset 2.5. Networking Interface
2.1. Memory Interface x
2.1.1. SDRAM Signals
2.5. Networking Interface x
2.5.1. Clock Signals 2.5.2. Data Interface and Signals 2.5.3. Control and Status Signals
1. Overview
2. FIM and AFU Parameter Data
3. FPGA Interface Manager (FIM) Resource Utilization
4. Document Revision History for FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

2.1. Memory Interface

The Intel® FPGA PAC with Intel® Arria® 10 GX FPGA features two DDR4 SDRAM memory banks, each of 4 GB capacity. They can be used by the AFU as a local workspace for large datasets. Each bank can be accessed independently by the AFU. Each memory bank interface is 64-bits and operates at 1066 MHz DDR.

Table 1.  Local Memory Interface Specifications
Parameter Value
Memory Protocol DDR4-SDRAM
AFU Interface Type Avalon™ Memory Mapped Interface ( Avalon® -MM)
Number of Memory Interfaces 2
Density per Memory Interface 4 GB
AFU-Accessible Memory Address Bus Width 27-bit
AFU-accessible Memory Data Width 512-bit
Interface Frequency 266 MHz
Maximum Burst Size 64 beats
Address Mapping CS-CID-Row-Bank-Col-BG
Level Two Title