FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683292
Date 8/18/2021
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. FIM and AFU Parameter Data 3. FPGA Interface Manager (FIM) Resource Utilization 4. Document Revision History for FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA
2. FIM and AFU Parameter Data x
2.1. Memory Interface 2.2. Core Cache Interface (CCI-P) Interface 2.3. Clocks 2.4. Reset 2.5. Networking Interface
2.1. Memory Interface x
2.1.1. SDRAM Signals
2.5. Networking Interface x
2.5.1. Clock Signals 2.5.2. Data Interface and Signals 2.5.3. Control and Status Signals
1. Overview
2. FIM and AFU Parameter Data
3. FPGA Interface Manager (FIM) Resource Utilization
4. Document Revision History for FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

2.5. Networking Interface

The networking interface provides one QSFP that can be configured to 4x10 GbE or 40 GbE.

Table 6.  Network Interface Specifications
Parameter Value Notes
Rate Supported 8x10GbE or 40 GbE -
Layers Supported PHY Physical Coding Sublayer (PCS) + Physical Medium Attachment (PMA) Sublayer
Note: For more information about the Networking Interface for the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA, please refer to the Networking Interface for Open Programmable Acceleration Engine: Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA.
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