FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683292
Date 8/18/2021
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. FIM and AFU Parameter Data 3. FPGA Interface Manager (FIM) Resource Utilization 4. Document Revision History for FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA
2. FIM and AFU Parameter Data x
2.1. Memory Interface 2.2. Core Cache Interface (CCI-P) Interface 2.3. Clocks 2.4. Reset 2.5. Networking Interface
2.1. Memory Interface x
2.1.1. SDRAM Signals
2.5. Networking Interface x
2.5.1. Clock Signals 2.5.2. Data Interface and Signals 2.5.3. Control and Status Signals
1. Overview
2. FIM and AFU Parameter Data
3. FPGA Interface Manager (FIM) Resource Utilization
4. Document Revision History for FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

2.5.1. Clock Signals

The clocks of the partial reconfiguration (PR) HSSI Interface synchronize the unified data interface between the MAC IP and the HSSI PHY. The signal directions listed for HSSI ports are from the perspective of the FIM. The signals listed below are identical for both QSFP28 interfaces.
Table 7.  Clock Signals
Port Name Width Direction Description
f2a_tx_clk 1 Output

4x10GBASE-R Mode: A 156.25 MHz clock derived from the HSSI PHY’s clock generation block (CGB) tx_pma_div_clkout clock output. All transmit data and control from the MAC to the HSSI PHY is synchronous to f2a_tx_clk.

40GBASE-SR4 Mode: A 312.5 MHz clock derived from the HSSI PHY’s CGB tx_pma_div_clkout clock output. All transmit data and control from the MAC/PHY to the HSSI PHY is synchronous to f2a_tx_clk.

f2a_tx_clkx2 1 Output

4x10GBASE-R Mode: A 312.5 MHz clock derived from the HSSI PHY’s CGB tx_pma_div_clkout clock output and phase-aligned with f2a_tx_clk.

40GBASE-SR4 Mode:A 312.5 MHz clock derived from the PHY’s CGB tx_pma_div_clkout clock output and phase-aligned with f2a_tx_clk.

f2a_tx_locked 1 Output

4x10GBASE-R Mode: Locked status for f2a_tx_clk and f2a_tx_clkx2.

40GBASE-SR4 Mode: Locked status for f2a_tx_clk and f2a_tx_clkx2.

f2a_rx_clk_ln0 1 Output

4x10GBASE-R Mode: A 156.25 MHz clock derived from the HSSI PHY’s transmitter and receive CDR PLL clock input reference. All receive data and control from the HSSI PHY to the MAC is synchronous to f2a_rx_clk_ln0.

40GBASE-SR4 Mode: A 312.5 MHz clock derived from the HSSI PHY’s receive CDR in lane 0. All receive data and control from the HSSI PHY to the MAC/PHY is synchronous to f2a_rx_clk_ln0.

f2a_rx_clkx2_ln0 1 Putput

4x10GBASE-R Mode: A 312.5 MHz clock derived from the HSSI PHY’s transmitter and receive CDR PLL clock input reference and phase-aligned with f2a_rx_clk_ln0.

40GBASE-SR4 Mode: A 312.5 MHz clock derived from the HSSI PHY’s receive CDR in lane 0 and phase-aligned with f2a_rx_clk_ln0.

f2a_rx_locked_ln0 1 Output

4x10GBASE-R Mode: Locked status for f2a_rx_clk_ln0 and f2a_rx_clkx2_ln0.

40GBASE-SR4 Mode: Locked status for f2a_rx_clk_ln0 and f2a_rx_clkx2_ln0.

f2a_rx_clk_ln4 1 Output

4x10GBASE-R Mode: Reserved

40GBASE-SR4 Mode: Reserved

f2a_rx_locked_ln4 1 Output

4x10GBASE-R Mode: Reserved

40GBASE-SR4 Mode: Reserved

Level Two Title