FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683292
Date 8/18/2021
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. FIM and AFU Parameter Data 3. FPGA Interface Manager (FIM) Resource Utilization 4. Document Revision History for FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA
2. FIM and AFU Parameter Data x
2.1. Memory Interface 2.2. Core Cache Interface (CCI-P) Interface 2.3. Clocks 2.4. Reset 2.5. Networking Interface
2.1. Memory Interface x
2.1.1. SDRAM Signals
2.5. Networking Interface x
2.5.1. Clock Signals 2.5.2. Data Interface and Signals 2.5.3. Control and Status Signals
1. Overview
2. FIM and AFU Parameter Data
3. FPGA Interface Manager (FIM) Resource Utilization
4. Document Revision History for FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

2.5.3. Control and Status Signals

This set of ports on the hssi interface provide for HSSI PHY receive Physical Medium Attachment (PMA) clock data recovery (CDR) lock sequencing control, PCS status, and transceiver loopback control. The signaling behavior conforms to the Intel® Arria® 10 FPGA Transceiver Native PHY IP with enhanced PCS. The below table cross references the hssi port names to the Native PHY IP port names.

Table 9.  Control and Status Signals
Port Name Width Direction Clock Domain Native PHY IP Port Name
a2f_rx_seriallpbken 4 Input Async rx_seriallpbken
a2f_rx_set_locktoref 4 Input Async rx_set_locktoref
f2a_rx_is_lockedtoref 4 Output Async rx_is_lockedtoref
a2f_rx_set_locktodata 4 Input Async rx_set_locktodata
f2a_rx_enh_blk_lock 4 Output f2a_rx_clk_ln0 rx_enh_blk_lock
f2a_rx_enh_highber 4 Output f2a_rx_clk_ln0 rx_enh_highber
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