AN 806: Hierarchical Partial Reconfiguration Tutorial: for Intel® Arria® 10 GX FPGA Development Board

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ID 683278
Date 2/04/2021
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Document Table of Contents
Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History for Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Sub-module Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Adding the Partial Reconfiguration Controller IP Step 6: Defining Personas Step 7: Creating Revisions Step 8: Compiling the Base Revision Step 9: Preparing the PR Implementation Revisions for Parent PR Partition Step 10: Preparing the PR Implementation Revisions for Child PR Partitions Step 11: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Adding the Partial Reconfiguration Controller IP x
Updating the Top-Level Design
Step 7: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 11: Programming the Board x
Programming the Child PR Region Troubleshooting PR Programming Errors
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board

Updating the Top-Level Design

To update the top.sv file with the PR_IP instance:
  1. To add the PR_IP instance to the top-level design, uncomment the following code block in the top.sv file: 
    pr_ip u_pr_ip
    (
        .clk           (clock),
        .nreset        (1'b1),
        .freeze        (freeze),
        .pr_start      (1'b0),            // ignored for JTAG
        .status        (pr_ip_status),
        .data          (16'b0),
        .data_valid    (1'b0),
        .data_ready    ()
    );
  2. To force the output ports to logic 1 during reconfiguration, use the freeze control signal output from PR_IP. However, to observe continuous blinking of the LED from the parent PR partition while PR programming the child partition, the freeze control signal does not turn off led_two_on. Ensure that the pr_led_two_on is directly assigned to led_two_on_w. led_three_on_w must choose between logic 1 and pr_led_three_on, based on the freeze signal. Uncomment the following lines of code:
    assign led_two_on_w = ? 1'b1 : pr_led_two_on;
assign led_three_on_w = freeze ? 1'b1 : pr_led_three_on;
  3. To assign an instance of the default parent persona (blinking_led), update the top.sv file with the following block of code:
    blinking_led u_blinking_led
   (
      .clock         (clock),
      .counter       (count_d),
      .led_two_on    (pr_led_two_on),
      .led_three_on  (pr_led_three_on)

   );
Figure 9. Partial Reconfiguration IP Core Integration
Level Two Title