AN 806: Hierarchical Partial Reconfiguration Tutorial: for Intel® Arria® 10 GX FPGA Development Board

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ID 683278
Date 2/04/2021
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Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History for Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Sub-module Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Adding the Partial Reconfiguration Controller IP Step 6: Defining Personas Step 7: Creating Revisions Step 8: Compiling the Base Revision Step 9: Preparing the PR Implementation Revisions for Parent PR Partition Step 10: Preparing the PR Implementation Revisions for Child PR Partitions Step 11: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Adding the Partial Reconfiguration Controller IP x
Updating the Top-Level Design
Step 7: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 11: Programming the Board x
Programming the Child PR Region Troubleshooting PR Programming Errors
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board

Step 5: Adding the Partial Reconfiguration Controller IP

Add the partial reconfiguration controller IP core to your project to reconfigure the PR partition. This IP core allows you to reconfigure the PR partition over a JTAG connection. Follow these steps to add the IP core to your project:
  1. In the Intel® Quartus® Prime IP catalog, Type Partial Reconfiguration Controller.
  2. Double-click the Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 FPGA IP from the IP library. The parameter editor appears.
    Figure 8. Partial Reconfiguration Controller IP Core Parameters
  3. In the New IP Variant dialog box, type pr_ip as the file name and click Create. Retain the following default parameterization for pr_ip:
    • Use as partial reconfiguration internal host is on.
    • Enable JTAG debug mode is on.
    • Enable freeze interface is on.
    • Enable Avalon-MM slave interface option is off.
    • Enable hierarchical PR support option is on.
    • Enable bitstream compatibility check option is on.
  4. In the parameter editor, click the Generate HDL button, and then exit the parameter editor without generating the system. The parameter editor creates the pr_ip.ip IP variation file, and adds the file to the project.
Note:
  1. If you are copying the pr_ip.ip file from the hpr folder, manually edit the blinking_led.qsf file to include the following line:
    set_global_assignment -name IP_FILE pr_ip.ip
  2. Place the IP_FILE assignment after the SDC_FILE assignments (jtag.sdc and blinking_led.sdc) in your blinking_led.qsf file. This ordering ensures appropriate constraining of the Partial Reconfiguration IP core.
    Note: To detect the clocks, the .sdc file for the PR IP must follow any .sdc that creates the clocks that the IP core uses. You facilitate this order by ensuring the .ip file for the PR IP core comes after any .ip files or .sdc files used to create these clocks in the .qsf file for your Intel® Quartus® Prime project revision. For more information, refer to Timing Constraints section in the Partial Reconfiguration IP Core User Guide.
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