Visible to Intel only — GUID: ipx1488919238675
Ixiasoft
Step 1: Getting Started
Step 2: Creating a Child Level Sub-module
Step 3: Creating Design Partitions
Step 4: Allocating Placement and Routing Region for PR Partitions
Step 5: Adding the Partial Reconfiguration Controller IP
Step 6: Defining Personas
Step 7: Creating Revisions
Step 8: Compiling the Base Revision
Step 9: Preparing the PR Implementation Revisions for Parent PR Partition
Step 10: Preparing the PR Implementation Revisions for Child PR Partitions
Step 11: Programming the Board
Modifying an Existing Persona
Adding a New Persona to the Design
Visible to Intel only — GUID: ipx1488919238675
Ixiasoft
Reference Design Walkthrough
The following steps describe the application of partial reconfiguration to a flat design. The tutorial uses the Intel® Quartus® Prime Pro Edition software for the Intel Arria® 10 GX FPGA development board:
- Step 1: Getting Started
- Step 2: Creating a Child Level Sub-module
- Step 3: Creating Design Partitions
- Step 4: Allocating Placement and Routing Region for PR Partitions
- Step 5: Adding the Partial Reconfiguration Controller IP
- Step 6: Defining Personas
- Step 7: Creating Revisions
- Step 8: Compiling the Base Revision
- Step 9: Preparing the PR Implementation Revisions for Parent PR Partition
- Step 10: Preparing the PR Implementation Revisions for Child PR Partitions
- Step 11: Programming the Board
- Step 1: Getting Started
- Step 2: Creating a Child Level Sub-module
- Step 3: Creating Design Partitions
- Step 4: Allocating Placement and Routing Region for PR Partitions
- Step 5: Adding the Partial Reconfiguration Controller IP
- Step 6: Defining Personas
- Step 7: Creating Revisions
- Step 8: Compiling the Base Revision
- Step 9: Preparing the PR Implementation Revisions for Parent PR Partition
- Step 10: Preparing the PR Implementation Revisions for Child PR Partitions
- Step 11: Programming the Board
- Modifying an Existing Persona
- Adding a New Persona to the Design