Visible to Intel only — GUID: lox1488919208775
Ixiasoft
Step 1: Getting Started
Step 2: Creating a Child Level Sub-module
Step 3: Creating Design Partitions
Step 4: Allocating Placement and Routing Region for PR Partitions
Step 5: Adding the Partial Reconfiguration Controller IP
Step 6: Defining Personas
Step 7: Creating Revisions
Step 8: Compiling the Base Revision
Step 9: Preparing the PR Implementation Revisions for Parent PR Partition
Step 10: Preparing the PR Implementation Revisions for Child PR Partitions
Step 11: Programming the Board
Modifying an Existing Persona
Adding a New Persona to the Design
Visible to Intel only — GUID: lox1488919208775
Ixiasoft
Reference Design Overview
This reference design consists of one 32-bit counter. At the board level, the design connects the clock to a 50MHz source, and connects the output to four LEDs on the FPGA. Selecting the output from the counter bits in a specific sequence causes the LEDs to blink at a specific frequency.
Figure 1. Flat Reference Design without PR Partitioning