AN 806: Hierarchical Partial Reconfiguration Tutorial: for Intel® Arria® 10 GX FPGA Development Board

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ID 683278
Date 2/04/2021
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Document Table of Contents
Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History for Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Sub-module Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Adding the Partial Reconfiguration Controller IP Step 6: Defining Personas Step 7: Creating Revisions Step 8: Compiling the Base Revision Step 9: Preparing the PR Implementation Revisions for Parent PR Partition Step 10: Preparing the PR Implementation Revisions for Child PR Partitions Step 11: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Adding the Partial Reconfiguration Controller IP x
Updating the Top-Level Design
Step 7: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 11: Programming the Board x
Programming the Child PR Region Troubleshooting PR Programming Errors
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board

Step 8: Compiling the Base Revision

Before you begin:
  1. Run the PR bitstream ID init script using the following command:
    quartus_sh -t prpof_id_mif_gen.tcl init
    This command allows the Intel® Quartus® Prime software to assign bitstream IDs to child PR regions, for bitstream compatibility check.
  2. Add the following assignments to blinking_led.qsf:
    set_global_assignment -name GENERATE_PR_RBF_FILE ON
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
    These assignments allow the Assembler to automatically generate the required PR bitstreams.

To compile the base revision:

  1. To compile the base revision, click Processing > Start Compilation. Alternatively, the following command compiles the base revision: 
    quartus_sh --flow compile  blinking_led -c blinking_led
    On successful compilation, the blinking_led_static.qdb file is generated in the output_files directory.
  2. To regenerate the base .sof file with the proper bitstream IDs for the child PR regions, run the PR bitstream ID update script using the following command: 
    quartus_sh -t prpof_id_mif_gen.tcl update
  3. Verify generation of the following the bitstream files:
    Table 5.  Generated Files
    Name Type Description
    output_files/blinking_led.sof Base programming file Used to program the FPGA with the static logic, along with the default personas for the parent and child PR regions.
    output_files/blinking_led.pr_parent_partition.rbf PR bitstream file for parent PR partition Used to program the default persona for the parent PR region.
    output_files/blinking_led.pr_parent_partition.pr_partition.rbf PR bitstream file for child PR partition Used to program the default persona for the child PR region.
    <project_directory>/blinking_led_static.qdb .qdb database file Finalized database file used to import the static region.
    <project_directory>/pr_parent_partition_default_final.qdb .qdb database file Finalized database file used to import the default parent PR partition.
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