AN 806: Hierarchical Partial Reconfiguration Tutorial: for Intel® Arria® 10 GX FPGA Development Board
Visible to Intel only — GUID: zby1488919227877
Ixiasoft
Visible to Intel only — GUID: zby1488919227877
Ixiasoft
Step 7: Creating Revisions
From this base revision, you create other revisions each implementation of the PR region. All PR implementation revisions must use the same top-level placement and routing results from the base revision.
To compile the PR design, you must create a PR implementation revision of the correct type for each PR persona. The following revision types are available:
- Partial Reconfiguration - Base
- Partial Reconfiguration - Persona Implementation
The following table lists the revision name and the revision type for each of the revisions you create in this tutorial:
Revision Name | Revision Type |
---|---|
blinking_led.qsf | Partial Reconfiguration - Base |
hpr_child_default.qsf | Partial Reconfiguration - Persona Implementation |
hpr_child_slow.qsf | Partial Reconfiguration - Persona Implementation |
hpr_child_empty.qsf | Partial Reconfiguration - Persona Implementation |
hpr_parent_slow_child_default.qsf | Partial Reconfiguration - Persona Implementation |
hpr_parent_slow_child_slow.qsf | Partial Reconfiguration - Persona Implementation |
Revision Name | Parent Persona Behavior | Child Persona Behavior |
---|---|---|
hpr_child_default.qsf | Fast blinking | Fast blinking |
hpr_child_slow.qsf | Fast blinking | Slow blinking |
hpr_child_empty.qsf | Fast Blinking | No blinking (always ON) |
hpr_parent_slow_child_default.qsf | Slow blinking | Fast blinking |
hpr_parent_slow_child_slow.qsf | Slow blinking | Slow blinking |