AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines

Download PDF
ID 683262
Date 3/12/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Platform Design Strategy for 56G PAM4 Channels 3. Document Revision History for AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines
2. Platform Design Strategy for 56G PAM4 Channels x
2.1. Intel® Stratix® 10 E-Tile Transceiver Channel Usage Mode 2.2. Intel® Stratix® 10 E-Tile Signaling - PAM4 vs. NRZ (PAM2) 2.3. PCB Design Flow
2.3. PCB Design Flow x
2.3.1. Design Target at 56 Gbps PAM4 Standard 2.3.2. PCB Materials and Stackup Design 2.3.3. FPGA PCB Design 2.3.4. PCB Pre-Layout Simulation Phase 2.3.5. PCB Post-Layout Simulation Phase
2.3.2. PCB Materials and Stackup Design x
2.3.2.1. Insertion Loss 2.3.2.2. Return Loss 2.3.2.3. Package Loss and Crosstalk 2.3.2.4. PCB Via Design 2.3.2.5. PCB Connector 2.3.2.6. Cable Usage in PCB Design
2.3.3. FPGA PCB Design x
2.3.3.1. FPGA PCB Breakout Design and Reference 2.3.3.2. P/N De-skew Strategy on Differential Pairs 2.3.3.3. Crosstalk - NEXT and FEXT in Differential Pairs
1. Introduction
2. Platform Design Strategy for 56G PAM4 Channels
3. Document Revision History for AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines

2.3.2.5. PCB Connector

Connectors are unavoidable in PCB board design. Hence, the PCB connector footprint must be optimized and tuned to reach the trace target impedance and have less discontinuity or reflection. Here are some tips that you can follow to optimize the PCB connector footprint:
  • Optimize the PCB connector footprint while following the connector vendor’s guideline.
  • Provide the PCB stackup and material information for the connector vendor to optimize the PCB footprint based on the channel impedance requirement.
  • Make sure the connector model boundary is defined clearly.
  • The connector model from the vendor usually includes the vendor’s reference PCB footprint.
  • Check if the connector model from the vendor includes the worst-case geometry, i.e. the pad stub of the mated edge card.

The following figure shows a QSFP connector as an example in the PCB connector footprint optimization.

Figure 12. QSFP Connector and PCB Footprint Optimization

Co-simulation must be done with the connector in an E/M tool solver. In the pre-layout phase, provide the PCB stackup and materials to the connector vendor for preliminary footprint optimization. In the post-layout phase, provide the routed PCB footprint to the connector vendor along with the final co-simulation with connector. Make sure to define a clear boundary for the final post-layout model for the end-to-end channel simulation.

Level Two Title