AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines

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ID 683262
Date 3/12/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Platform Design Strategy for 56G PAM4 Channels 3. Document Revision History for AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines
2. Platform Design Strategy for 56G PAM4 Channels x
2.1. Intel® Stratix® 10 E-Tile Transceiver Channel Usage Mode 2.2. Intel® Stratix® 10 E-Tile Signaling - PAM4 vs. NRZ (PAM2) 2.3. PCB Design Flow
2.3. PCB Design Flow x
2.3.1. Design Target at 56 Gbps PAM4 Standard 2.3.2. PCB Materials and Stackup Design 2.3.3. FPGA PCB Design 2.3.4. PCB Pre-Layout Simulation Phase 2.3.5. PCB Post-Layout Simulation Phase
2.3.2. PCB Materials and Stackup Design x
2.3.2.1. Insertion Loss 2.3.2.2. Return Loss 2.3.2.3. Package Loss and Crosstalk 2.3.2.4. PCB Via Design 2.3.2.5. PCB Connector 2.3.2.6. Cable Usage in PCB Design
2.3.3. FPGA PCB Design x
2.3.3.1. FPGA PCB Breakout Design and Reference 2.3.3.2. P/N De-skew Strategy on Differential Pairs 2.3.3.3. Crosstalk - NEXT and FEXT in Differential Pairs
1. Introduction
2. Platform Design Strategy for 56G PAM4 Channels
3. Document Revision History for AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines

2.3.1. Design Target at 56 Gbps PAM4 Standard

Understanding the PAM4 standards is the key in the PAM4 PCB design flow. You must evaluate your channel loss budgets by using a loss estimate for each channel element in an end-to-end channel.

Below are the recommended channel losses for different standards:

50/56G PAM4 - Refer to each standard for the loss requirement:
  • IEEE802.3bs
  • IEEE802.3cd
  • OIF CEI-56G-VSR
  • OIF CEI-56G-MR
  • OIF CEI-56G-LR
25/28G NRZ - Refer to each standard for the loss requirement:
  • IEEE802.3bj
  • IEEE802.3by
  • OIF CEI-28G-VSR
  • OIF CEI-28G-MR
  • OIF CEI-28G-LR

The following figure shows the channel insertion loss (IL) budget calculation for an end-to-end (TP0 to TP5) 200GBASE-CR4 channel, with the IL estimate at the Nyquist frequency for each channel element provided. Intel recommends that you estimate the minimum and maximum insertion loss allocations for each element of the channel (transmitter to receiver) carefully to meet the link standard (e.g. IEEE802.3cd).

Figure 6. Example of an end-to-end 200GBASE-CR4 Channel Loss Estimation

The boundaries of each element (i.e. connectors and cables) in the above example must be carefully defined.

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