AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines

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ID 683262
Date 3/12/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Platform Design Strategy for 56G PAM4 Channels 3. Document Revision History for AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines
2. Platform Design Strategy for 56G PAM4 Channels x
2.1. Intel® Stratix® 10 E-Tile Transceiver Channel Usage Mode 2.2. Intel® Stratix® 10 E-Tile Signaling - PAM4 vs. NRZ (PAM2) 2.3. PCB Design Flow
2.3. PCB Design Flow x
2.3.1. Design Target at 56 Gbps PAM4 Standard 2.3.2. PCB Materials and Stackup Design 2.3.3. FPGA PCB Design 2.3.4. PCB Pre-Layout Simulation Phase 2.3.5. PCB Post-Layout Simulation Phase
2.3.2. PCB Materials and Stackup Design x
2.3.2.1. Insertion Loss 2.3.2.2. Return Loss 2.3.2.3. Package Loss and Crosstalk 2.3.2.4. PCB Via Design 2.3.2.5. PCB Connector 2.3.2.6. Cable Usage in PCB Design
2.3.3. FPGA PCB Design x
2.3.3.1. FPGA PCB Breakout Design and Reference 2.3.3.2. P/N De-skew Strategy on Differential Pairs 2.3.3.3. Crosstalk - NEXT and FEXT in Differential Pairs
1. Introduction
2. Platform Design Strategy for 56G PAM4 Channels
3. Document Revision History for AN 875: Intel® Stratix® 10 E-Tile PCB Design Guidelines

2.2. Intel® Stratix® 10 E-Tile Signaling - PAM4 vs. NRZ (PAM2)

The Intel® Stratix® 10 E-Tile enables both PAM4 and NRZ signaling.

PAM4 signaling uses four distinct voltage levels to encode two bits of data in every symbol, thereby doubling the bandwidth of the link without increasing the fundamental frequency.

The following figure shows illustrations of PAM4 signaling and NRZ signaling.

Figure 3. PAM4 vs NRZ Signaling

In PAM4 mode, the noise margin is reduced compared to NRZ mode since in PAM4, the amplitude between adjacent signal levels is only one-third that of NRZ. This intrinsic loss compared to NRZ reduces the noise margin by approximately -9.5 dB. Therefore, noise margin is a critical consideration for the design of high-speed links using PAM4 signaling.

The following figure shows signal modulation examples in an Intel® Stratix® 10 E-Tile channel design for both NRZ and PAM4 signaling modes.

Figure 4.  Intel® Stratix® 10 E-Tile NRZ and PAM4 Modulation Examples

Due to the reduced noise margin in PAM4, the peak-to-peak eye opening is smaller than that in NRZ mode.

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