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1.1. Stratix V Family Variants
1.2. Stratix V Features Summary
1.3. Stratix V Family Plan
1.4. Low-Power Serial Transceivers
1.5. PCIe Gen3, Gen2, and Gen1 Hard IP (Embedded HardCopy Block)
1.6. External Memory and GPIO
1.7. Adaptive Logic Module
1.8. Clocking
1.9. Fractional PLL
1.10. Embedded Memory
1.11. Variable Precision DSP Block
1.12. Power Management
1.13. Incremental Compilation
1.14. Enhanced Configuration and CvP
1.15. Automatic Single Event Upset Error Detection and Correction
1.16. HardCopy V Devices
1.17. Ordering Information
1.18. Document Revision History
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1. Stratix V Device Overview
Altera’s 28-nm Stratix® V FPGAs include innovations such as an enhanced core architecture, integrated transceivers up to 28.05 gigabits per second (Gbps), and a unique array of integrated hard intellectual property (IP) blocks.
With these innovations, Stratix V FPGAs deliver a new class of application-targeted devices optimized for:
- Bandwidth-centric applications and protocols, including PCI Express® (PCIe®) Gen3
- Data-intensive applications for 40G/100G and beyond
- High-performance, high-precision digital signal processing (DSP) applications
Stratix V devices are available in four variants (GT, GX, GS, and E), each targeted for a different set of applications. For higher volume production, you can prototype with Stratix V FPGAs and use the low-risk, low-cost path to HardCopy® V ASICs.
Section Content
Stratix V Family Variants
Stratix V Features Summary
Stratix V Family Plan
Low-Power Serial Transceivers
PCIe Gen3, Gen2, and Gen1 Hard IP (Embedded HardCopy Block)
External Memory and GPIO
Adaptive Logic Module
Clocking
Fractional PLL
Embedded Memory
Variable Precision DSP Block
Power Management
Incremental Compilation
Enhanced Configuration and CvP
Automatic Single Event Upset Error Detection and Correction
HardCopy V Devices
Ordering Information
Document Revision History
Related Information