Intel® Cyclone® 10 LP Device Datasheet

Download PDF
ID 683251
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 LP Device Datasheet
Intel® Cyclone® 10 LP Device Datasheet x
Operating Conditions Power Consumption Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for the Intel® Cyclone® 10 LP Device Datasheet
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot or Undershoot Voltage Recommended Operating Conditions ESD Performance DC Characteristics I/O Standard Specifications
DC Characteristics x
Supply Current Bus Hold OCT Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor Hot-Socketing Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standard Specifications Single-Ended SSTL and HSTL I/O Reference Voltage Specifications Single-Ended SSTL and HSTL I/O Standards Signal Specifications Differential SSTL I/O Standard Specifications Differential HSTL I/O Standard Specifications Differential I/O Standard Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance
Core Performance Specifications x
Clock Tree Specifications PLL Specifications Embedded Multiplier Specifications Memory Block Specifications
Periphery Performance x
High-Speed I/O Specifications Duty Cycle Distortion Specifications OCT Calibration Timing Specification IOE Programmable Delay
High-Speed I/O Specifications x
RSDS Transmitter Timing Specifications Emulated RSDS_E_1R Transmitter Timing Specifications Mini-LVDS Transmitter Timing Specifications True LVDS Transmitter Timing Specifications Emulated LVDS Transmitter Timing Specifications LVDS Receiver Timing Specifications
Configuration Specifications x
JTAG Timing Parameters Active Configuration Mode Specifications AS Configuration Timing Passive Configuration Mode Specifications PS Configuration Timing FPP Configuration Timing
Intel® Cyclone® 10 LP Device Datasheet

RSDS Transmitter Timing Specifications

Table 24.  RSDS Transmitter Timing Specifications for Intel® Cyclone® 10 LP Devices

Applicable for true RSDS and emulated RSDS_E_3R transmitter.

True RSDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Emulated RSDS transmitter is supported at the output pin of all I/O Banks.

Symbol Mode C6 I7 C8, A7 I8 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
fHSCLK
(input clock frequency) ×10 5 — 180 5 — 155.5 5 — 155.5 5 — 155.5 MHz
×8 5 — 180 5 — 155.5 5 — 155.5 5 — 155.5 MHz
×7 5 — 180 5 — 155.5 5 — 155.5 5 — 155.5 MHz
×4 5 — 180 5 — 155.5 5 — 155.5 5 — 155.5 MHz
×2 5 — 180 5 — 155.5 5 — 155.5 5 — 155.5 MHz
×1 5 — 360 5 — 311 5 — 311 5 — 311 MHz
Device operation in Mbps ×10 100 — 360 100 — 311 100 — 311 100 — 311 Mbps
×8 80 — 360 80 — 311 80 — 311 80 — 311 Mbps
×7 70 — 360 70 — 311 70 — 311 70 — 311 Mbps
×4 40 — 360 40 — 311 40 — 311 40 — 311 Mbps
×2 20 — 360 20 — 311 20 — 311 20 — 311 Mbps
×1 10 — 360 10 — 311 10 — 311 10 — 311 Mbps
tDUTY — 45 — 55 45 — 55 45 — 55 45 — 55 %
Transmitter channel-to-channel skew (TCCS) — — — 200 — — 200 — — 200 — — 200 ps
Output jitter
(peak to peak) — — — 500 — — 500 — — 550 — — 600 ps
tRISE 20 – 80%, CLOAD = 5 pF — 500 — — 500 — — 500 — — 500 — ps
tFALL 20 – 80%, CLOAD = 5 pF — 500 — — 500 — — 500 — — 500 — ps
tLOCK 41 — — — 1 — — 1 — — 1 — — 1 ms
41 tLOCK is the time required for the PLL to lock from the end-of-device configuration.
Level Two Title